My Inquiry
My Account
NXP Semiconductors 74AUP1T97GN,132
- Part No.:
- 74AUP1T97GN,132
- Manufacturer:
- NXP Semiconductors
- Category:
- Translators, Level Shifters
- Package:
- Datasheet:
-
74AUP1T97GN,132.pdf
- Description:
- NEXPERIA 74AUP1T97GN - LOGIC CIR
- Quantity:
- Payment:
- Shipping:
Inventory:124,300
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74AUP1T97GN,132 from Nexperia is a single-supply, low-power configurable logic gate with Schmitt-trigger inputs and voltage-level translation capability. It functions as a programmable 3-input logic element (MUX, AND, OR, NAND, NOR, inverter, or buffer) across 2.3 V to 3.6 V supply, supports partial power-down via IOFF, and operates from –40 °C to +125 °C in the XSON6 (SOT1115) package. It enables level-shifting between 1.8 V logic and 3.3 V systems.
For engineers reviewing the 74AUP1T97GN,132 datasheet, 74AUP1T97GN,132 pinout, 74AUP1T97GN,132 application, or 74AUP1T97GN,132 equivalent, this device delivers configurable logic functionality with ultra-low static current (≤1.5 μA), robust ESD protection (HBM >5 kV), and guaranteed operation under partial power-down conditions - critical for battery-powered IoT nodes, industrial sensor interfaces, and mixed-voltage FPGA I/O bridging.
Technical Context
The 74AUP1T97GN,132 implements a 3-bit function-select architecture where inputs A, B, and C determine logic behavior via truth table mapping - enabling dynamic reconfiguration without external components. Its Schmitt-trigger inputs provide hysteresis (0.10–0.60 V) for noise immunity in noisy environments.
IOFF circuitry actively disables outputs when VCC = 0 V, blocking backflow current up to ±0.75 μA at 125 °C. The device complies with JEDEC standards JESD8-12 through JESD8C and supports overvoltage-tolerant inputs up to 3.6 V independent of VCC.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 2.3 V to 3.6 V - enables direct integration into 2.5 V/3.3 V systems while accepting 1.8 V inputs. |
| ICC (max) | 1.5 μA at 125 °C - ensures sub-microwatt standby power for always-on edge sensors. |
| IOFF Leakage | ±0.75 μA at 125 °C - prevents damaging backfeed during hot-swap or partial system shutdown. |
| Propagation Delay | 1.4–7.5 ns (CL = 5–30 pF, VCC = 2.3–3.6 V) - supports timing-critical signal routing in high-speed digital interfaces. |
| Hysteresis Voltage | 0.10–0.60 V - rejects noise spikes on slow-rising signals in industrial control wiring. |
| ESD Protection | HBM >5000 V, CDM >1000 V - eliminates need for external TVS diodes in handheld and field-deployed equipment. |
| Operating Temperature | –40 °C to +125 °C - qualified for under-hood automotive, motor drive, and industrial PLC applications. |
Pinout & Package
XSON6 package (SOT1115): extremely thin small outline, no leads, 6-terminal surface-mount device measuring 0.9 × 1.0 × 0.35 mm - optimized for space-constrained PCBs in wearables and compact modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (B) | Data input | One of three configurable logic inputs; accepts 0–3.6 V regardless of VCC level. |
| 2 (GND) | Ground reference | 0 V return path for all internal logic and output drivers; must be low-impedance. |
| 3 (A) | Data input | Primary logic select input; determines function configuration with B and C per Table 4. |
| 4 (Y) | Output | Single-ended CMOS output capable of driving 4 mA at 3.0 V; supports rail-to-rail swing. |
| 5 (VCC) | Supply voltage | Power rail for internal logic and output stage; IOFF activates when VCC = 0 V. |
| 6 (C) | Data input | Third logic input; completes 3-bit function code; compatible with 1.8 V CMOS levels. |
Key Features
| Feature | Design Value |
|---|---|
| Configurable logic function | Single device replaces seven discrete gates (MUX, AND, OR, NAND, NOR, inverter, buffer) - reduces BOM count and layout area. |
| Voltage-level translation | Accepts 1.8 V inputs while operating at 3.3 V VCC - eliminates need for external level shifters in mixed-voltage MCU peripherals. |
| IOFF partial power-down | Outputs go high-impedance when VCC = 0 V - prevents back-current damage during hot-plug or sleep-mode isolation. |
| Schmitt-trigger inputs | Input hysteresis ≥0.10 V - suppresses chatter on slow or noisy signals from mechanical switches or long traces. |
| Ultra-low ICC | Max 1.5 μA at 125 °C - extends battery life in coin-cell-powered remote sensors beyond 10 years. |
Applications
| Industrial Sensor Interface | FPGA I/O Bridging |
|---|---|
|
Use Scenario: Interfacing 1.8 V MEMS pressure sensors to 3.3 V industrial PLC input modules with long cable runs. IC Role / Device Role / Timing Role: Level-translating logic gate configured as a buffer with Schmitt-trigger input to reject EMI-induced glitches. Use Value: Eliminates external level shifter and RC filter; maintains signal integrity without added propagation delay. |
Use Scenario: Adapting heterogeneous voltage domains between FPGA banks (1.2 V/1.8 V) and legacy 3.3 V peripheral buses. IC Role / Device Role / Timing Role: Configurable MUX/gate enabling flexible signal routing and voltage domain isolation during partial reconfiguration. Use Value: Reduces interposer complexity and board layer count by consolidating logic and level translation in one 0.9 mm × 1.0 mm footprint. |
| Automotive Body Control | IoT Edge Node Power Management |
|
Use Scenario: Debouncing and translating signals from 5 V mechanical door latch switches to 3.3 V microcontroller GPIOs in body control modules. IC Role / Device Role / Timing Role: Inverter with Schmitt-trigger input used as a noise-immune switch interface; IOFF protects during ignition-off sleep mode. Use Value: Prevents false wake-ups from ESD transients; meets AEC-Q100 Grade 1 temperature requirements without derating. |
Use Scenario: Enabling/disabling power rails to BLE SoCs and environmental sensors based on motion-detection events in battery-powered asset trackers. IC Role / Device Role / Timing Role: NAND gate configured as an active-low enable controller with ultra-low ICC (<1.5 μA) minimizing quiescent drain. Use Value: Extends shelf life and operational runtime by reducing system standby current by >30% versus discrete MOSFET solutions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar configurable logic gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC1G97GW,125 | Wider VCC range (1.65–5.5 V); higher ICC (max 10 μA); no IOFF; TSSOP6 package (1.25 mm width). | Better suited for 5 V legacy systems but lacks power-down safety for hot-swap use cases. | Select when interfacing with 5 V logic and board space allows larger TSSOP6 footprint. |
| SN74LVC1G97DBVR | Same VCC range (1.65–5.5 V); no IOFF; higher propagation delay (min 3.5 ns); SOT-23-6 package. | Higher pin capacitance (4.5 pF vs. 1.7 pF) limits high-frequency signal integrity in dense layouts. | Choose only if existing design uses SOT-23-6 land pattern and IOFF is not required. |
Compared with 74LVC1G97GW,125 and SN74LVC1G97DBVR, the 74AUP1T97GN,132 uniquely combines ultra-low ICC, guaranteed IOFF, and sub-1 mm² XSON6 packaging - making it the sole option for thermally constrained, battery-sensitive, and partial-power-down–critical designs.
Availability
74AUP1T97GN,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control units, and IoT edge node power management requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1T97GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions with focus on efficiency, reliability, and miniaturization for automotive, industrial, and consumer markets.
The 74AUP1T97GN,132 belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family - engineered specifically for energy-constrained, mixed-voltage applications demanding robust noise immunity and safe partial power-down operation.
FAQ
Can the 74AUP1T97GN,132 operate with VCC = 0 V while inputs remain at 3.3 V?
Yes - its overvoltage-tolerant inputs accept up to 3.6 V regardless of VCC state. When VCC = 0 V, IOFF activates, placing Y in high-impedance mode and limiting input leakage to ±0.75 μA at 125 °C, preventing back-current damage to upstream drivers.
How is logic function selected on the 74AUP1T97GN,132?
Function selection is determined by the voltage states of inputs A, B, and C per Table 4 in the datasheet: e.g., A=L/B=L/C=L configures a logic LOW output; A=H/B=L/C=H configures a 2-input MUX. No external programming or configuration pins are needed - behavior is purely combinational.
What is the minimum load capacitance the 74AUP1T97GN,132 can drive reliably?
The device is characterized down to CL = 5 pF, with typical propagation delay of 1.4 ns (VCC = 3.6 V, VI = 3.0–3.6 V). Driving loads below 5 pF is permissible but may reduce noise margin; output rise/fall times remain monotonic and within specification across the full 0–30 pF test range.
Does the 74AUP1T97GN,132 require external pull-up or pull-down resistors on unused inputs?
No - all inputs (A, B, C) can be directly tied to VCC or GND without external resistors. Internal input structure tolerates static DC biasing, and Schmitt-trigger thresholds ensure clean switching even with slow edges or floating conditions avoided by hard-wiring.
74AUP1T97GN,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- *
- Package/Case:
- Packaging:
- Bulk
- Product Status:
- Active
- Translator Type:
- -
- Channel Type:
- -
- Number of Circuits:
- -
- Channels per Circuit:
- -
- Voltage - VCCA:
- -
- Voltage - VCCB:
- -
- Input Signal:
- -
- Output Signal:
- -
- Output Type:
- -
- Data Rate:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Features:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
74AUP1T97GN,132 FAQ
1.How can I place an order for 74AUP1T97GN,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1T97GN,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1T97GN,132 reliable?
The price and inventory of 74AUP1T97GN,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1T97GN,132 is usually 5 days.
3.What payment methods are accepted for 74AUP1T97GN,132?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1T97GN,132 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP1T97GN,132?
74AUP1T97GN,132 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1T97GN,132 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1T97GN,132?
For technical support, including 74AUP1T97GN,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1T97GN,132 requirements.
6.How does Aetrix verify that 74AUP1T97GN,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP1T97GN,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1T97GN,132 meets industry standards.
7.What is the process for return or replacement of 74AUP1T97GN,132?
All 74AUP1T97GN,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1T97GN,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1T97GN,132 part is unused and in its original packaging.
Return procedure for 74AUP1T97GN,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP1T97GN,132 Tags
-
74LVC1T45GW,125
Nexperia USA Inc.
-
74LVCH2T45DC,125
Nexperia USA Inc.
-
SN74LVC1T45DBVR
Texas Instruments
-
SN74LVC1T45DRLR
Texas Instruments
-
SN74LVC1T45DPKR
Texas Instruments
-
SN74LVC2T45DCTR
Texas Instruments
-
74LVC2T45GT,115
Nexperia USA Inc.
-
SN74LVC1T45YZPR
Texas Instruments
-
LSF0102DCUR
Texas Instruments
-
SN74LVC1T45DCKR
Texas Instruments
-
TXS0102DCTR
Texas Instruments
-
FXLP34P5X
onsemi
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
