Nexperia USA Inc. 74AUP1T97GW,125

Overview

74AUP1T97GW,125 from Nexperia is a low-power configurable logic gate with Schmitt-trigger inputs and voltage-level translation capability, supporting 2.3 V to 3.6 V supply operation. It implements MUX, AND, OR, NAND, NOR, inverter, or buffer functions via its 3-bit configuration input (A/B/C), delivers <1.5 μA max ICC at 25 °C, features IOFF for partial power-down protection, and operates across –40 °C to +125 °C - used in mixed-voltage I/O bridging between 1.8 V and 3.3 V domains in industrial control interfaces.

For engineers reviewing the 74AUP1T97GW,125 datasheet, 74AUP1T97GW,125 pinout, 74AUP1T97GW,125 application, or 74AUP1T97GW,125 equivalent, this device serves as a single-gate logic configurator with level-shifting and robust noise immunity in space-constrained TSSOP6 packaging - critical for legacy-to-modern voltage domain interfacing, sensor signal conditioning, and low-power MCU peripheral gating.

Technical Context

The 74AUP1T97GW,125 uses Schmitt-trigger inputs with hysteresis (0.15–0.56 V) and threshold voltages adjustable by VCC (VT+ = 0.75–1.19 V, VT− = 0.46–0.85 V), enabling reliable switching in noisy environments and compatibility with 1.8 V logic driving 3.3 V systems. Its IOFF circuit actively disables outputs during power-down, preventing backflow current when VCC = 0 V.

Function selection is determined by the logic states of inputs A, B, and C per Table 4 and Table 5 - no external configuration pins or registers are required. All inputs tolerate up to 3.6 V regardless of VCC, and output drive strength is specified at ±2.3 mA (VCC = 2.3 V) and ±4.0 mA (VCC = 3.0 V).

Key Specifications

Pinout & Package

TSSOP6 package (SOT363-2): plastic thin shrink small outline, 6-lead, 1.25 mm body width, 0.65 mm pitch, moisture sensitivity level 1.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G97DBVR and 74LVC1G98GW,125, the 74AUP1T97GW,125 uniquely combines sub-μA static current, Schmitt-trigger noise immunity, and IOFF-enabled power-down safety - making it optimal for energy-sensitive, electrically harsh, or thermally demanding embedded interfaces where reliability outweighs voltage range breadth.

Availability

74AUP1T97GW,125 is available at Aetrix Electronics and suitable for industrial sensor interface, automotive body control, IoT edge node power management, and medical diagnostic equipment requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1T97GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a leading semiconductor manufacturer specializing in high-performance, energy-efficient logic, analog, and discrete components for automotive, industrial, and consumer markets.

The 74AUP1T97GW,125 belongs to Nexperia's Advanced Ultra Low Power (AUP) logic family, designed specifically for low-voltage, low-noise, mixed-signal interfacing in space- and power-constrained embedded systems.

FAQ

Can the 74AUP1T97GW,125 operate with VCC = 2.5 V while accepting 1.8 V inputs?

Yes. The device is fully specified from 2.3 V to 3.6 V VCC and supports overvoltage-tolerant inputs up to 3.6 V. At VCC = 2.5 V, its Schmitt-trigger thresholds (VT+ ≈ 0.85 V, VT− ≈ 0.55 V) ensure clean switching from 1.8 V logic, enabling robust level translation without external components.

What happens to the Y output when VCC is removed?

When VCC = 0 V, the IOFF circuit disables the output, limiting leakage current to ±0.75 μA over –40 °C to +125 °C. The Y pin enters a high-impedance state, preventing back-current flow into powered downstream circuitry - critical for safe hot-swap and power-domain isolation.

How is the logic function selected on the 74AUP1T97GW,125?

Function selection is determined solely by the logic states of inputs A, B, and C per the truth table in Section 7.1. For example, A=H/B=L/C=L configures a 2-input MUX; A=H/B=H/C=L configures an AND gate. No external programming or clocking is required - configuration is static and immediate upon input stabilization.

Is the 74AUP1T97GW,125 pin-compatible with other 6-pin logic gates in TSSOP6?

No. While the SOT363-2 (TSSOP6) footprint is standard, the 74AUP1T97GW,125 has a unique pin assignment: Pin 1=B, Pin 3=A, Pin 6=C, Pin 4=Y, Pin 5=VCC, Pin 2=GND. Substituting with non-configurable gates (e.g., 74LVC1G00) requires PCB redesign due to differing signal mapping.