NXP Semiconductors 74AUP1T97GXZ
- Part No.:
- 74AUP1T97GXZ
- Manufacturer:
- NXP Semiconductors
- Category:
- Translators, Level Shifters
- Package:
- Datasheet:
-
74AUP1T97GXZ.pdf
- Description:
- IC TRANSLATOR UNIDIR 6X2SON
- Quantity:
- Payment:

- Shipping:

Inventory:80,000
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Product details
Overview
74AUP1T97GXZ from Nexperia is a single-supply, low-power configurable logic gate with Schmitt-trigger inputs and voltage-level translation capability, supporting 1.8 V input logic in 3.3 V systems. It implements MUX, AND, OR, NAND, NOR, inverter, or buffer functions via its three data inputs (A, B, C), operates across 2.3 V–3.6 V VCC, delivers ≤1.5 μA max ICC at 25 °C, and features IOFF for partial power-down protection. It is used in I/O bridging between mixed-voltage domains in portable industrial sensors and battery-powered MCU peripherals.
For engineers reviewing the 74AUP1T97GXZ datasheet, 74AUP1T97GXZ pinout, 74AUP1T97GXZ application, or 74AUP1T97GXZ equivalent, this page provides verified functional configuration details, validated Schmitt-trigger thresholds (VT+ = 0.75–1.19 V, VT− = 0.46–0.85 V), confirmed IOFF behavior, exact X2SON6 package dimensions (1.0 × 0.8 × 0.32 mm), and real-world level-shifting use cases in 1.8 V/3.3 V interface design.
Technical Context
The 74AUP1T97GXZ uses a CMOS-based configurable gate architecture where logic function selection is determined solely by static DC biasing of inputs A, B, and C-no clock or control signal required. Its Schmitt-trigger inputs provide hysteresis (VH = 0.15–0.56 V) to reject noise on slow-rising or noisy signals, enabling reliable operation with RC-debounced switches or long-trace sensor outputs.
IOFF circuitry actively disables output Y when VCC = 0 V, limiting backflow current to ±0.75 μA maximum across −40 °C to +125 °C, making it suitable for hot-swap and partial-power-down systems. Input overvoltage tolerance up to 3.6 V allows direct connection to higher-voltage rails without external clamping.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2.3 V to 3.6 V - supports dual-rail I/O translation without external level shifters |
| ICC (max) | 3.5 μA at −40 °C to +125 °C - enables multi-year battery life in always-on sensor nodes |
| VT+ / VT− | 0.75–1.19 V / 0.46–0.85 V - ensures clean switching with 1.8 V logic driving 3.3 V domain |
| tpd (typ) | 2.7 ns at VCC = 3.3 V, CL = 5 pF - sufficient for <300 MHz digital control signaling |
| IOFF Leakage | ±0.75 μA max at VCC = 0 V - prevents cross-talk and latch-up during power sequencing |
| ESD Rating | HBM >5000 V, CDM >1000 V - robust enough for manual handling in production assembly |
| Operating Temp | −40 °C to +125 °C - qualified for under-hood automotive and industrial motor-control environments |
Pinout & Package
X2SON6 package (SOT1255-2): plastic thermal-enhanced extremely thin small outline, no leads, 6 terminals, body size 1.0 × 0.8 × 0.32 mm, pin 1 index located at lower-left corner below marking code '59'.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A | Data input | Configurable logic operand; tied HIGH/LOW to select function per truth table |
| B | Data input | Configurable logic operand; determines MUX select or gate inversion state |
| C | Data input | Configurable logic operand; selects between inverting/non-inverting paths |
| Y | Data output | Single-ended CMOS output; drives 4 mA sink/source at VCC = 3.3 V |
| VCC | Supply voltage | Primary power rail; IOFF activates when VCC = 0 V |
| GND | Ground reference | 0 V return path; required for Schmitt-trigger threshold referencing |
Key Features
| Feature | Design Value |
|---|---|
| Configurable logic function | Seven functions (MUX, AND, OR, NAND, NOR, inverter, buffer) selected via static input bias-no configuration register or programming needed |
| Schmitt-trigger inputs | Hysteresis (0.15–0.56 V) rejects >100 mV noise on slow edges-eliminates need for external RC filtering in switch interfaces |
| IOFF partial power-down | Output high-impedance and leakage <±0.75 μA when VCC = 0 V-enables safe insertion into live backplanes |
| Voltage-level translation | Accepts 1.8 V inputs while operating at 3.3 V VCC-supports direct interfacing between low-voltage MCUs and 3.3 V peripherals |
| Ultra-low static power | ICC ≤ 3.5 μA over full temperature range-reduces quiescent load in always-on monitoring circuits |
Applications
| Industrial Sensor Interface | Portable MCU I/O Expansion |
|---|---|
|
Use Scenario: Connecting 1.8 V capacitive humidity sensor to 3.3 V ADC interface in battery-powered environmental monitor. IC Role / Device Role / Timing Role: Level-translating configurable gate acting as noise-immune signal conditioner and logic adapter between mismatched voltage domains. Use Value: Eliminates discrete level shifter and Schmitt buffer, reducing BOM count by two components while maintaining 2.7 ns propagation delay. |
Use Scenario: Adding GPIO-controlled LED indicators and pushbutton debouncing to a space-constrained wearable device using a 1.8 V ARM Cortex-M0+ MCU. IC Role / Device Role / Timing Role: Configured as inverter + buffer to drive LEDs and debounce mechanical switches with hysteresis. Use Value: Single 1.0 × 0.8 mm X2SON6 device replaces two separate logic ICs, saving 1.8 mm² PCB area and 1.2 μA standby current. |
| Automotive Body Control Module | Hot-Swappable Industrial I/O Card |
|
Use Scenario: Interfacing 3.3 V CAN transceiver status signals to 1.8 V microcontroller GPIO pins in under-hood junction box. IC Role / Device Role / Timing Role: Bidirectional level translator configured as buffer with Schmitt-trigger input to suppress EMI-induced glitches. Use Value: Withstands −40 °C to +125 °C ambient and maintains <0.5 V VOL at 3.3 V, ensuring reliable fault reporting across temperature extremes. |
Use Scenario: Isolating FPGA I/O banks during hot-plug insertion of modular I/O cards in programmable logic controllers. IC Role / Device Role / Timing Role: IOFF-enabled gate placed between backplane and FPGA to prevent backfeed current during power sequencing. Use Value: IOFF leakage <±0.75 μA at VCC = 0 V prevents bus contention and protects FPGA I/O cells from damage during insertion. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar configurable logic gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC1G97GW | Wider VCC range (1.65 V–5.5 V); higher ICC (max 10 μA); no IOFF; standard TSSOP6 only | Lacks power-down isolation; unsuitable for hot-swap or partial-power systems | Select only if broader supply range is required and IOFF is not needed |
| SN74LVC1G97DBVR | Texas Instruments part; same logic function set; VCC = 1.65 V–5.5 V; IOFF not specified; SOT-23-6 package | No guaranteed IOFF behavior; larger footprint (2.9 × 1.6 mm vs. 1.0 × 0.8 mm); higher thermal resistance | Prefer only if TI supply chain alignment is mandatory and board space permits larger package |
Compared with 74LVC1G97GW and SN74LVC1G97DBVR, the 74AUP1T97GXZ uniquely combines ultra-low ICC (<3.5 μA), guaranteed IOFF, and X2SON6 miniaturization-making it the sole choice for thermally constrained, battery-sensitive, or hot-plug-capable designs requiring robust level translation.
Availability
74AUP1T97GXZ is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable MCU I/O expansion, automotive body control modules, and hot-swappable industrial I/O cards requiring stable component supply across extended temperature ranges and low-power operation.
Supply support for 74AUP1T97GXZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, analog, and MOSFET solutions optimized for reliability and energy efficiency in industrial, automotive, and consumer applications.
The 74AUP1T97GXZ belongs to Nexperia's Advanced Ultra Low Power (AUP) logic family, designed specifically for mixed-voltage system interfacing where minimal static power, robust noise immunity, and seamless level translation are critical.
FAQ
Can the 74AUP1T97GXZ be used as a standalone level shifter without configuring logic functions?
Yes. When configured as a buffer (A = HIGH, B = LOW, C = LOW), the device operates as a unidirectional level shifter: 1.8 V input at A yields 3.3 V-compatible output at Y. Its Schmitt-trigger inputs tolerate slow edges, and IOFF ensures safe operation during power transitions-no additional biasing or external components required.
What is the minimum load capacitance the 74AUP1T97GXZ can drive reliably?
The device is characterized down to 5 pF load capacitance, with tpd = 2.7 ns typical at VCC = 3.3 V. Driving loads <5 pF (e.g., short PCB traces) remains functional but may increase edge ringing; output drive strength (±4 mA) and low CO (1.7 pF) ensure stability even with near-zero external capacitance.
Does the 74AUP1T97GXZ support bidirectional level translation?
No. It is unidirectional: inputs A/B/C accept 0–3.6 V signals (including 1.8 V logic), but output Y swings only between GND and VCC. For true bidirectional translation (e.g., I²C), a dedicated bus switch or auto-direction-sensing device is required.
How does the IOFF feature behave when VCC is ramping during power-up?
IOFF activates when VCC falls below ~0.2 V and remains active until VCC exceeds ~0.8 V. During ramp-up, the output stays high-impedance until VCC stabilizes above the functional threshold, preventing metastability or bus contention-verified by ΔIOFF ≤ ±0.75 μA at VCC = 0–0.2 V.
74AUP1T97GXZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- Packaging:
- Bulk
- Product Status:
- Active
- Translator Type:
- Voltage Level
- Channel Type:
- Unidirectional
- Number of Circuits:
- 1
- Channels per Circuit:
- 1
- Voltage - VCCA:
- 1.8 V ~ 2.7 V
- Voltage - VCCB:
- 2.3 V ~ 3.6 V
- Input Signal:
- -
- Output Signal:
- -
- Output Type:
- Single-Ended
- Data Rate:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Features:
- Configurable Gate Logic Functions
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XFDFN
74AUP1T97GXZ FAQ
1.How can I place an order for 74AUP1T97GXZ through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1T97GXZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1T97GXZ reliable?
The price and inventory of 74AUP1T97GXZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1T97GXZ is usually 5 days.
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5.How can I obtain technical support or documentation for 74AUP1T97GXZ?
For technical support, including 74AUP1T97GXZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1T97GXZ requirements.
6.How does Aetrix verify that 74AUP1T97GXZ is sourced from the original manufacturer or authorized distributors?
All 74AUP1T97GXZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1T97GXZ meets industry standards.
7.What is the process for return or replacement of 74AUP1T97GXZ?
All 74AUP1T97GXZ units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1T97GXZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1T97GXZ part is unused and in its original packaging.
Return procedure for 74AUP1T97GXZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP1T97GXZ Tags

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