Nexperia USA Inc. 74AUP1T97UKAZ

Overview

74AUP1T97UKAZ from Nexperia is a single-supply, dual-input configurable logic gate with Schmitt-trigger inputs, operating from 0.8 V to 3.6 V, delivering 2.1 ns propagation delay at 3.3 V and supporting I_OFF partial power-down protection. It enables level translation in low-power IoT sensor interfaces.

For engineers reviewing the 74AUP1T97UKAZ datasheet, 74AUP1T97UKAZ pinout, 74AUP1T97UKAZ application, or 74AUP1T97UKAZ equivalent, key selection criteria include supply voltage range, propagation delay vs. V_CC, input hysteresis width, I_OFF behavior, and SC-70-6 package thermal resistance.

Technical Context

This device implements a single 2-input logic gate whose function (AND, OR, NAND, NOR, XOR, XNOR) is determined by external configuration of its A/B/C pins. It uses CMOS technology with rail-to-rail input switching thresholds and hysteresis (typically 0.12 V at V_CC = 3.3 V) to reject noise on slow or noisy signals.

The I_OFF circuitry disables current flow when V_CC = 0 V, preventing back-driving of powered circuitry during hot insertion or partial power-down. Output drive strength is ±4 mA at V_CC = 3.3 V with guaranteed VOH/VOL across the full voltage range.

Key Specifications

Pinout & Package

Supplied in SC-70-6 (SOT-363) package: 2.2 mm × 2.2 mm footprint, 0.65 mm pitch, 0.95 mm height, JEDEC MO-203-DA compliant, with θ_JA = 290 °C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G97DCKR and 74LVC1G98GW,125, the 74AUP1T97UKAZ offers lowest quiescent current and guaranteed I_OFF, making it optimal for ultra-low-power, hot-swap-capable designs where supply sequencing is non-deterministic.

Availability

74AUP1T97UKAZ is available at Aetrix Electronics and suitable for industrial sensor interfaces, IoT edge node wake-up circuits, and low-voltage level translation requiring stable component supply across long-lifecycle programs.

Supply support for 74AUP1T97UKAZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability essential semiconductors for automotive, industrial, and consumer applications.

The 74AUP logic family targets ultra-low-power, wide-voltage configurable logic for battery-operated and mixed-supply systems, emphasizing I_OFF, small footprint, and robust noise immunity.

FAQ

Can the 74AUP1T97UKAZ operate with V_CC = 1.2 V?

Yes. The device is fully specified from 0.8 V to 3.6 V, including guaranteed propagation delay, output drive, and Schmitt-trigger hysteresis at 1.2 V. At this voltage, t_PD is 5.8 ns and I_OH/I_OL is ±2.5 mA, meeting 1.2 V logic interface requirements.

What happens to the output when V_CC is disconnected?

When V_CC = 0 V, the I_OFF circuitry isolates all inputs and outputs. No current flows into or out of any pin, preventing back-powering of the device or loading of upstream drivers, which is critical during hot-swap or partial power-down sequences.

How is the logic function selected on the 74AUP1T97UKAZ?

The logic function is set by static voltage levels applied to pins A, B, and C at power-up. For example, tying A = HIGH, B = LOW, and C = HIGH configures the gate as an OR function. The complete mapping is defined in Table 2 of the Nexperia datasheet (document number 74AUP1T97).

Is the 74AUP1T97UKAZ RoHS-compliant and halogen-free?

Yes. The 74AUP1T97UKAZ meets RoHS Directive 2011/65/EU and is certified halogen-free per IEC 61249-2-21. The SC-70-6 package uses lead-free matte tin terminal finish and complies with Nexperia's standard environmental specifications.