NXP Semiconductors 74AUP1T98GF,132

Overview

74AUP1T98GF,132 from Nexperia is a single-supply, low-power configurable logic gate with Schmitt-trigger inputs and voltage-level translation capability. It functions as a reconfigurable 3-input logic element (MUX, AND, OR, NAND, NOR, inverter, or buffer) via static input configuration, operates across 2.3 V to 3.6 V, delivers ≤1.5 μA max ICC, and supports partial power-down via IOFF. It enables level-shifting between 1.8 V and 3.3 V domains in portable I/O expansion and mixed-voltage sensor interface circuits.

For engineers reviewing the 74AUP1T98GF,132 datasheet, 74AUP1T98GF,132 pinout, 74AUP1T98GF,132 application, or 74AUP1T98GF,132 equivalent, this device is selected for ultra-low static power, robust noise immunity in noisy industrial environments, precise hysteresis control (0.15–0.56 V), and guaranteed IOFF protection during system sleep states - critical for battery-powered IoT nodes and always-on peripheral controllers.

Technical Context

The 74AUP1T98GF,132 implements a single-stage CMOS configurable gate with three user-defined inputs (A, B, C) controlling function selection and one output (Y). Its Schmitt-trigger inputs provide hysteresis (VH = 0.15–0.56 V) and support direct connection to 1.8 V logic while powered from 3.3 V, enabling seamless voltage translation without external biasing.

IOFF circuitry actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA across –40 °C to +125 °C, satisfying JEDEC JESD78 Class II Level B latch-up immunity (>100 mA) and ensuring safe hot-insertion in modular systems.

Key Specifications

Pinout & Package

74AUP1T98GF,132 is packaged in SOT886 (XSON6), a 6-terminal, leadless, 1.0 × 1.45 × 0.5 mm plastic package with wettable flanks for automated optical inspection. Pin 1 is marked by a beveled corner; terminals are arranged in a 2×3 grid with GND at position 2, VCC at 5, and signal pins A (3), B (1), C (6), Y (4).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with 74LVC1G98GW,125 and SN74LVC1G97DBVR, the 74AUP1T98GF,132 uniquely combines ultra-low ICC (<1.5 μA), guaranteed IOFF, and programmable hysteresis - making it the sole option for energy-constrained, mixed-voltage, noise-prone embedded systems requiring functional safety during power transitions.

Availability

74AUP1T98GF,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, IoT peripheral expansion, automotive body control modules, and medical wearable power sequencing requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1T98GF,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-volume, high-reliability logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and thermally constrained applications, delivering nanowatt static power and robust noise immunity without sacrificing speed or integration density.

FAQ

Can 74AUP1T98GF,132 translate 1.2 V logic to 3.3 V?

No. The device's Schmitt-trigger inputs require minimum VIH of 0.60 V (at VCC = 2.3 V) and maximum VIL of 0.64 V (at VCC = 2.7 V), but its input threshold voltages scale with VCC and are not specified below 1.65 V per JESD8-7. Driving from 1.2 V violates recommended operating conditions and risks unreliable switching.

What is the maximum capacitive load the output can drive reliably?

The output is characterized up to 30 pF load capacitance with propagation delays specified from 1.3 ns (VCC = 3.6 V, CL = 5 pF) to 11.9 ns (VCC = 2.3 V, CL = 30 pF). Driving >30 pF may increase delay unpredictably and degrade edge rate; for >50 pF loads, add a series resistor or buffer stage.

Does IOFF activate automatically when VCC drops below a threshold?

Yes. IOFF engages when VCC falls below approximately 0.2 V, disabling the output driver and limiting leakage to ±0.75 μA regardless of input/output voltage (0–3.6 V). This occurs without external control signals and remains active until VCC rises above ~0.8 V.

How is the logic function selected - by hardware wiring or serial programming?

Function selection is purely hardware-based via static DC voltage levels applied to inputs A, B, and C. No clock, serial interface, or configuration memory is involved. The truth table (Table 4) and function selection guide (Table 5) define exact pin states required for each gate type (e.g., C=H,B=L,A=L → NAND).