Nexperia USA Inc. 74AUP1T98GN,132

Overview

74AUP1T98GN,132 from Nexperia is a single-supply, low-power configurable logic gate with Schmitt-trigger inputs and voltage-level translation capability. It functions as a reconfigurable 3-input logic cell (MUX, AND, OR, NAND, NOR, inverter, or buffer) across V_CC = 2.3 V to 3.6 V, supports partial power-down via IOFF, and operates from –40 °C to +125 °C in the XSON6 (SOT1115) package. It enables level-shifting between 1.8 V and 3.3 V domains in mixed-voltage I/O interfaces.

For engineers reviewing the 74AUP1T98GN,132 datasheet, 74AUP1T98GN,132 pinout, 74AUP1T98GN,132 application, or 74AUP1T98GN,132 equivalent, this device serves as a space-constrained, ultra-low-static-power solution for I/O bridging, signal conditioning, and flexible logic configuration in battery-powered and thermally constrained embedded systems.

Technical Context

The 74AUP1T98GN,132 implements a 3-input combinational logic block where inputs A, B, and C define function selection via truth table mapping - enabling dynamic reconfiguration without external programming. Its Schmitt-trigger inputs provide hysteresis (V_H = 0.10–0.60 V) for noise immunity and clean switching on slow or noisy signals.

IOFF circuitry actively disables outputs during V_CC = 0 V, limiting backflow current to ±0.75 μA, while overvoltage-tolerant inputs accept up to 3.6 V regardless of V_CC. Propagation delay ranges from 1.3 ns (V_CC = 3.6 V, C_L = 5 pF) to 11.9 ns (V_CC = 2.3 V, C_L = 30 pF), supporting high-speed interface adaptation.

Key Specifications

Pinout & Package

XSON6 package (SOT1115): extremely thin small outline, no leads, 6-terminal surface-mount package measuring 0.9 mm × 1.0 mm × 0.35 mm - optimized for high-density PCB layouts and automated assembly.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G98DRYR and 74LVC1G99GW,125, the 74AUP1T98GN,132 uniquely combines ultra-low ICC (<3.5 μA), integrated Schmitt inputs, and IOFF - making it the sole option for battery-critical, noise-prone, or multi-rail hot-swap applications requiring minimal footprint.

Availability

74AUP1T98GN,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical devices, automotive body control modules, and smart home hubs requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1T98GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable logic, discrete, and MOSFET solutions with leadership in efficiency, miniaturization, and quality for mass-market electronics.

The 74AUP1T98GN,132 belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family - engineered specifically for energy-sensitive, space-constrained applications demanding robust noise immunity and seamless voltage-domain bridging.

FAQ

Can the 74AUP1T98GN,132 operate with V_CC = 1.8 V?

No. The 74AUP1T98GN,132 is specified only for V_CC = 2.3 V to 3.6 V per Table 7. At 1.8 V, VIH/VIL thresholds fall outside guaranteed logic levels, and ICC, propagation delay, and output drive are not characterized. Use SN74LVC1G98 for 1.65 V operation.

How is the logic function selected on the 74AUP1T98GN,132?

Function selection is determined solely by the DC voltage states applied to pins A, B, and C, per Table 4. For example, tying A = HIGH, B = LOW, C = LOW configures the device as an inverter (Y = NOT A). No clock, enable, or programming sequence is required - configuration is static and immediate.

Does the 74AUP1T98GN,132 require external pull-up or pull-down resistors on inputs?

No. All inputs tolerate direct connection to V_CC or GND per Section 1. Schmitt-trigger inputs eliminate need for external biasing, and internal design ensures valid logic states without floating inputs - simplifying PCB layout and reducing component count.

What is the maximum capacitive load the 74AUP1T98GN,132 can drive reliably?

The device is characterized up to C_L = 30 pF (Table 9), with t_pd increasing predictably (e.g., 11.9 ns max at V_CC = 2.3 V). Driving >30 pF may degrade timing margin and increase dynamic power; for heavier loads, add a dedicated buffer stage or reduce trace length and capacitance.