Nexperia USA Inc. 74AUP1T98GS,132

Overview

74AUP1T98GS,132 from Nexperia is a single-supply, low-power configurable logic gate with Schmitt-trigger inputs and voltage-level translation capability. It implements MUX, AND, OR, NAND, NOR, inverter, or buffer functions via 3-bit configuration (A/B/C inputs), operates from 2.3 V to 3.6 V, delivers ≤5.7 ns propagation delay at 2.3 V/5 pF, and supports partial power-down via IOFF. It enables level-shifting between 1.8 V logic and 3.3 V systems in space-constrained industrial sensor interfaces.

For engineers reviewing the 74AUP1T98GS,132 datasheet, 74AUP1T98GS,132 pinout, 74AUP1T98GS,132 application, or 74AUP1T98GS,132 equivalent, this device serves as a flexible, ultra-low-static-current (≤1.5 μA) logic reconfiguration element for mixed-voltage I/O bridging, noise-immune signal conditioning, and compact board-level logic synthesis where footprint and power are critical.

Technical Context

The 74AUP1T98GS,132 uses a CMOS-based configurable gate architecture with three independent data inputs (A, B, C) that define logic function selection through truth table mapping - not programmable memory or serial interface. Its Schmitt-trigger inputs provide hysteresis (0.10–0.60 V) for robust noise immunity across temperature and supply ranges.

IOFF circuitry actively disables outputs during power-down (VCC = 0 V), limiting backflow current to ±0.75 μA, while overvoltage-tolerant inputs accept up to 3.6 V regardless of VCC. The device is fully characterized from −40 °C to +125 °C and supports JEDEC-compliant voltage standards including JESD8-12 (0.8–1.3 V) and JESD8C (2.7–3.6 V).

Key Specifications

Pinout & Package

XSON6 package (SOT1202): extremely thin small outline, no leads, 6-terminal surface-mount, 1.0 × 1.0 × 0.35 mm body, wettable flank compatible.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G98DRYR and 74LVC1G97GV,125, the 74AUP1T98GS,132 uniquely combines Schmitt-trigger noise rejection, ultra-low ICC (<1.5 μA), and guaranteed IOFF behavior - making it the only option for battery-sensitive, noise-prone, or hot-swap-capable designs requiring both level translation and signal integrity.

Availability

74AUP1T98GS,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, low-power IoT nodes, modular PLC backplanes, and automotive body control modules requiring stable component supply, extended temperature operation, and consistent lead-time visibility.

Supply support for 74AUP1T98GS,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.

The 74AUP1T98GS,132 belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family, engineered specifically for space- and power-constrained applications requiring mixed-voltage interoperability, robust noise immunity, and fail-safe partial power-down behavior.

FAQ

What logic functions can the 74AUP1T98GS,132 implement?

The 74AUP1T98GS,132 implements seven logic functions - inverter, buffer, 2-input MUX (inverting), AND, OR, NAND, and NOR - determined solely by the voltage states applied to its three configuration inputs (A, B, C). No programming interface or non-volatile memory is involved; function selection is static and immediate upon power-up or input change.

Does the 74AUP1T98GS,132 support true bidirectional level translation?

No. The 74AUP1T98GS,132 supports unidirectional level translation only: inputs accept voltages down to 0.8 V (e.g., 1.8 V logic) while operating at VCC = 3.3 V, and the output swings rail-to-rail between GND and VCC. It does not auto-detect direction or translate output signals back to lower voltages.

How does the IOFF feature behave during power sequencing?

When VCC drops to 0 V, the IOFF circuit automatically disables the output driver, limiting leakage current to ±0.75 μA regardless of input or output voltage (0–3.6 V). This prevents backfeeding into a powered bus or damaging downstream components during staggered power-up/down sequences in multi-rail systems.

Can the 74AUP1T98GS,132 drive a 15 pF load at 3.0 V with sub-6 ns delay?

Yes. At VCC = 3.0 V, VI = 2.3–2.7 V, and CL = 15 pF, the typical propagation delay is 3.9 ns with a maximum of 5.7 ns across −40 °C to +125 °C - satisfying sub-6 ns timing requirements for high-speed digital control loops and real-time sensor sampling interfaces.