Nexperia USA Inc. 74AUP1T98GW,125

Overview

74AUP1T98GW,125 from Nexperia is a single-supply, low-power configurable logic gate with Schmitt-trigger inputs and voltage-level translation capability. It implements MUX, AND, OR, NAND, NOR, inverter, or buffer functions via its 3-bit input configuration (A/B/C), operates across 2.3 V to 3.6 V, supports partial power-down via IOFF, and enables 1.8 V logic interfacing in 3.3 V systems - used in mixed-voltage I/O bridging for industrial sensor interfaces and portable MCU peripherals.

For engineers reviewing the 74AUP1T98GW,125 datasheet, 74AUP1T98GW,125 pinout, 74AUP1T98GW,125 application, or 74AUP1T98GW,125 equivalent, this device is selected for ultra-low static current (<1.5 μA), robust noise immunity (hysteresis ≥0.25 V), level-shifting compatibility between 1.8 V and 3.3 V domains, and guaranteed operation from –40 °C to +125 °C in TSSOP6 packaging.

Technical Context

The 74AUP1T98GW,125 uses CMOS technology with Schmitt-trigger inputs enabling clean signal recovery from slow or noisy edges, and an IOFF circuit that disables outputs during power-down to prevent backflow current. Its function selection is determined solely by the logic states of inputs A, B, and C - no external configuration pins or control signals are required.

It achieves level translation by accepting input voltages down to 0.3 V (for VT−) and up to 3.6 V while operating from a single VCC supply, and maintains output drive strength (VOH ≥2.3 V at 2.3 V VCC, VOL ≤0.5 V at 3.0 V VCC) across its full temperature and voltage range.

Key Specifications

Pinout & Package

TSSOP6 package (SOT363-2): plastic thin shrink small outline, 6-lead, 1.25 mm body width, 0.65 mm lead pitch, exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G98DRYR and 74LVC1G97GW,125, the 74AUP1T98GW,125 uniquely combines ultra-low ICC, IOFF, Schmitt-trigger inputs, and level translation in one TSSOP6 device - making it the sole choice for energy-constrained, noise-prone, mixed-voltage applications requiring guaranteed power-down safety.

Availability

74AUP1T98GW,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable MCU peripheral bridges, and automotive body control modules requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1T98GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions, with leadership in automotive-qualified components and energy-efficient design.

The 74AUP1T98GW,125 belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family, engineered specifically for battery-powered and thermally constrained applications demanding sub-microamp quiescent current and robust mixed-voltage interoperability.

FAQ

Can the 74AUP1T98GW,125 operate with VCC = 1.8 V?

No. The 74AUP1T98GW,125 is specified only from 2.3 V to 3.6 V per Table 7. Operation below 2.3 V violates recommended conditions and may result in undefined logic states, increased propagation delay, or failure to meet VOH/VOL specifications. For 1.8 V systems, consider the 74AUP2G04 or similar AUP-series dual gates rated down to 0.8 V.

What happens to the Y output when VCC = 0 V and inputs are driven?

When VCC = 0 V, the IOFF circuit activates and forces Y into high-impedance state regardless of input voltages. Input pins remain overvoltage tolerant up to 3.6 V, and IOFF leakage is limited to ±0.75 μA across –40 °C to +125 °C - preventing backfeed current into powered-down sections of the system.

How is logic function selected on the 74AUP1T98GW,125?

Function selection is determined solely by the logic levels applied to inputs A (pin 3), B (pin 1), and C (pin 6), per Table 4. For example, A=L, B=L, C=L yields Y=H (inverting MUX mode); A=H, B=L, C=L yields Y=L (NAND mode). No external programming or clock is needed - configuration is static and immediate upon input stabilization.

Is the 74AUP1T98GW,125 pin-compatible with other 74AUP1Txx variants?

No. While sharing the same TSSOP6 footprint, the 74AUP1T98GW,125 has unique pin assignments: Y is on pin 4, VCC on pin 5, and C on pin 6. In contrast, 74AUP1T00 (dual inverter) places outputs on pins 2 and 5, and 74AUP1T57 (dual MUX) uses different input/output mappings - direct substitution will cause functional failure.