Nexperia USA Inc. 74AUP1T98GW-Q100H

Overview

74AUP1T98GW-Q100 from Nexperia is an automotive-grade, low-power configurable logic gate with Schmitt-trigger inputs and voltage-level translation capability. It implements MUX, AND, OR, NAND, NOR, inverter, or buffer functions via 3-bit input configuration (A/B/C), operates across 2.3 V to 3.6 V supply, supports partial power-down via IOFF, and delivers <1.5 μA max ICC at -40 °C to +125 °C - enabling robust signal conditioning in automotive body control modules.

For engineers reviewing the 74AUP1T98GW-Q100 datasheet, 74AUP1T98GW-Q100 pinout, 74AUP1T98GW-Q100 application, or 74AUP1T98GW-Q100 equivalent, this device serves as a single-supply, level-translating logic reconfigurable element for mixed-voltage I/O interfacing, noise-immune sensor signal routing, and power-aware subsystem isolation in AEC-Q100 Grade 1 environments.

Technical Context

This device integrates Schmitt-trigger inputs with programmable logic functionality using three data inputs (A, B, C) to select one of eight logic configurations. Its IOFF circuitry actively disables outputs during power-down, blocking backflow current when VCC = 0 V - critical for hot-swap and partial-power-down architectures.

It supports bidirectional voltage translation between 1.8 V logic domains and 3.3 V systems via hysteresis-controlled inputs (VT+ = 0.75–1.19 V, VT− = 0.46–0.85 V at VCC = 3.0–3.6 V) and rail-to-rail output drive (VOH ≥ 2.30 V, VOL ≤ 0.50 V at IO = ±4 mA), all while maintaining CMOS-level static power consumption.

Key Specifications

Pinout & Package

TSSOP6 (SOT363-2) package: plastic thin shrink small outline, 6-lead, 1.25 mm body width, 0.65 mm lead pitch, lead-free and RoHS compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G98DRYR and 74AUP1T97GW-Q100, the 74AUP1T98GW-Q100 uniquely combines automotive qualification, Schmitt-trigger noise immunity, and full 3-bit logic configurability - making it the sole option for AEC-Q100-compliant, mixed-voltage, reprogrammable logic nodes.

Availability

74AUP1T98GW-Q100 is available at Aetrix Electronics and suitable for automotive body control units, ADAS camera modules, infotainment I/O expansion, and electric power steering subsystems requiring stable component supply across extended temperature and long product lifecycles.

Supply support for 74AUP1T98GW-Q100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable logic, discrete, and MOSFET solutions optimized for automotive, industrial, and mobile applications.

The 74AUP1T98GW-Q100 belongs to Nexperia's AUP (Advanced Ultra-low Power) logic family, designed specifically for energy-efficient, AEC-Q100-compliant signal conditioning and interface bridging in next-generation automotive ECUs.

FAQ

What logic functions can be implemented with the 74AUP1T98GW-Q100?

The device implements eight logic functions via its three input pins (A, B, C): inverting 2-input MUX, NAND, NOR, AND, OR, buffer, and inverter. The function table in section 7 of the datasheet defines exact input combinations (e.g., CBA = 000 → Y = HIGH; CBA = 111 → Y = LOW), and all configurations operate with Schmitt-trigger inputs and level translation capability.

How does the IOFF feature protect the device during partial power-down?

When VCC = 0 V, the IOFF circuitry forces the output (Y) into high-impedance state regardless of input states, blocking reverse current flow from externally driven inputs or outputs. This prevents damage to powered subsystems and complies with JEDEC JESD78 Class II Level B latch-up immunity (>100 mA).

Can the 74AUP1T98GW-Q100 interface 1.8 V FPGA I/O with a 3.3 V microcontroller?

Yes - its Schmitt-trigger inputs accept 1.8 V logic levels while operating at VCC = 3.3 V, and its outputs swing rail-to-rail (VOH ≥ 2.6 V, VOL ≤ 0.44 V at IO = ±4 mA), meeting 3.3 V LVTTL input thresholds. No external level shifter is needed for bidirectional signal translation.

Is the 74AUP1T98GW-Q100 pin-compatible with other AUP-series single-gate devices?

No - it uses a unique 6-pin TSSOP6 (SOT363-2) pinout optimized for its 3-input + 1-output + VCC + GND configuration. Devices like 74AUP1G00 or 74AUP1G04 use different pin assignments (e.g., 5-pin SC-70) and lack the C input and configurability, making them non-interchangeable without PCB redesign.