My Inquiry
My Account
NXP Semiconductors 74AUP1Z04GW/C125
- Part No.:
- 74AUP1Z04GW/C125
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialty Logic
- Package:
- 6-TSSOP, SC-88, SOT-363
- Datasheet:
-
74AUP1Z04GW/C125.pdf
- Description:
- BUS DRIVER, AUP/ULP/V SERIES
- Quantity:
- Payment:
- Shipping:
Inventory:3,173
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74AUP1Z04GW/C125 from NXP Semiconductors is a low-power crystal oscillator driver IC integrating dual inverters (74AUP1GU04 + 74AUP1G04), enable control, and internal bias/pull-up resistors. It operates from 0.8 V to 3.6 V, delivers propagation delays as low as 0.7 ns (X1→X2, VCC = 3.0–3.6 V, CL = 5 pF), features IOFF for partial power-down, and supports −40 °C to +125 °C operation in SC-88 (SOT363) package - optimized for compact, stable clock generation in portable and automotive timing systems.
For engineers reviewing the 74AUP1Z04GW/C125 datasheet, 74AUP1Z04GW/C125 pinout, 74AUP1Z04GW/C125 application, or 74AUP1Z04GW/C125 equivalent, key selection criteria include its integrated Rbias (~1.62 MΩ typ), Schmitt-trigger EN input tolerance across full VCC range, IOFF-enabled Y-output isolation during power-down, and verified performance in Pierce oscillator topologies with load capacitance up to 30 pF.
Technical Context
The 74AUP1Z04GW/C125 implements a two-stage inverter-based Pierce oscillator core: the first stage (X1→X2) provides gain and phase inversion, while the second stage (X2→Y) buffers and isolates the output. Its internal Rbias sets the inverter's DC bias point near mid-supply to maximize linear-region gain, and the dedicated EN input (active LOW, Schmitt-triggered) controls oscillator enable/disable with X1 pulled HIGH via internal RPU when disabled.
IOFF circuitry actively disables output Y during VCC = 0 V, limiting backflow current to ±0.75 µA max, enabling safe partial power-down in mixed-voltage systems. The device's dynamic characteristics are specified across VCC = 0.8–3.6 V and Tamb = −40 °C to +125 °C, with propagation delay (X1→Y) ranging from 1.4 ns to 6.9 ns depending on VCC and CL (5–30 pF).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 0.8 V to 3.6 V - enables direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Propagation Delay (X1→X2) | 0.7 ns min (VCC = 3.0–3.6 V, CL = 5 pF) - ensures tight timing margins in high-frequency crystal oscillators. |
| Propagation Delay (X1→Y) | 1.4 ns min (VCC = 3.0–3.6 V, CL = 5 pF) - provides buffered, isolated clock output with predictable latency. |
| Bias Resistance (Rbias) | 1.07–3.11 MΩ - sets optimal DC operating point for crystal drive stability across temperature and voltage. |
| IOFF Leakage Current | ±0.75 µA max (VCC = 0 V) - prevents damaging backflow current during system power sequencing. |
| Operating Temperature | −40 °C to +125 °C - qualified for under-hood automotive and industrial control applications. |
| Input Capacitance (X1) | 1.3 pF typ - minimizes crystal load perturbation and supports high-Q resonator integration. |
Pinout & Package
74AUP1Z04GW/C125 uses the SC-88 (SOT363) plastic surface-mounted package: 6-lead, 2.2 mm × 1.8 mm × 1.1 mm body, 0.65 mm pitch, pin 1 indicator at lower-left corner below marking code "a4".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (EN) | Enable input (active LOW) | Schmitt-triggered control signal; drives device into low-power disable mode when HIGH, pulling X1 HIGH via internal RPU. |
| 2 (GND) | Ground reference | 0 V return path for all internal circuits and I/O; must be low-impedance for stable oscillator operation. |
| 3 (X1) | Inverter input | Primary crystal node connection; interfaces directly with one terminal of quartz resonator in Pierce configuration. |
| 4 (X2) | Inverter output | Feedback path to crystal; forms gain stage with X1; requires external C1/C2 load capacitors per crystal spec. |
| 5 (VCC) | Supply voltage | Power rail for both inverter stages and bias network; decoupling capacitor required near pin for noise immunity. |
| 6 (Y) | Buffered output | Isolated clock output with IOFF protection; drives downstream logic or clock distribution without loading oscillator core. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Rbias & RPU | Eliminates external bias resistors, reducing BOM count and PCB footprint while ensuring consistent crystal startup and amplitude control. |
| IOFF-enabled Y output | Allows safe power gating of downstream circuitry without risk of reverse current damage to the oscillator core. |
| Schmitt-trigger EN input | Accepts slow-rising/falling enable signals across full 0.8–3.6 V VCC range, simplifying control interface design. |
| Low dynamic power dissipation | CPD = 24.9 pF max (VCC = 3.0–3.6 V) enables sub-µW oscillator operation at 1 MHz, critical for battery-powered devices. |
| ESD robustness | HBM > 5000 V, CDM > 1000 V - withstands handling and board-level ESD events without latch-up or parametric shift. |
Applications
| Automotive Body Control Module | Industrial PLC Real-Time Clock |
|---|---|
Use Scenario: Generating precise 32.768 kHz or 1–20 MHz clock for microcontroller timing, CAN bus synchronization, and sensor sampling in vehicle door modules. IC Role / Device Role / Timing Role: Primary crystal oscillator driver in Pierce topology, providing low-jitter, temperature-stable clock with integrated enable for sleep/wake cycling. Use Value: Enables <1 µA standby current via EN-controlled disable and IOFF, meeting ISO 16750-2 quiescent current requirements. | Use Scenario: Supplying accurate system clock to ARM Cortex-M7-based PLC controllers operating in harsh factory environments (−40 °C to +85 °C). IC Role / Device Role / Timing Role: Low-noise, high-reliability clock source with internal biasing, eliminating external resistor drift and improving long-term frequency stability. Use Value: Reduces total oscillator component count by 3 (Rbias, RPU, pull-up), lowering assembly cost and improving MTBF over 10-year deployment. |
| Portable Medical Wearable | Smart Energy Meter MCU Clock |
Use Scenario: Driving 32.768 kHz tuning-fork crystal for RTC in ECG patch monitors powered by coin-cell batteries. IC Role / Device Role / Timing Role: Ultra-low-power oscillator core with 75 µA max ICC (EN = GND), supporting multi-year battery life. Use Value: Achieves <200 nA typical shutdown current (EN = HIGH) via internal RPU, extending battery runtime beyond 5 years. | Use Scenario: Providing metrology-grade timebase for anti-tampering secure MCU in ANSI C12.22-compliant smart meters. IC Role / Device Role / Timing Role: Temperature-compensated clock generator with −40 °C to +125 °C qualification and low phase noise (<10 % VCC overshoot). Use Value: Maintains ±20 ppm frequency accuracy over full temperature range without external TCXO, cutting BOM cost by 40 %. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar crystal oscillator driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74AUP1Z04GM | XSON6 (SOT886) package: 1.0 mm × 1.45 mm × 0.5 mm, leadless, smaller footprint than SC-88. | Preferred for ultra-dense layouts where board space is constrained; same electrical specs and pinout mapping. | Select when PCB real estate is premium and reflow profile supports XSON6. |
| 74LVC1G14GV | Single Schmitt-trigger inverter only; no integrated enable, Rbias, or RPU; requires external biasing components. | Suitable for discrete oscillator designs where flexibility outweighs integration benefit; lacks IOFF and wide-VCC Schmitt EN. | Choose only if existing design already uses external bias network and requires minimal gate count. |
Compared with 74AUP1Z04GM, the 74AUP1Z04GW/C125 offers identical functionality in a larger but more hand-solderable and test-probe-friendly SC-88 package; versus 74LVC1G14GV, it delivers complete oscillator integration - eliminating four external passives and enabling guaranteed startup across voltage/temperature extremes.
Availability
74AUP1Z04GW/C125 is available at Aetrix Electronics and suitable for automotive body electronics, industrial programmable logic controllers, and portable medical wearables requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP1Z04GW/C125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with headquarters in Eindhoven, Netherlands.
The 74AUP1Z04GW/C125 belongs to NXP's ultra-low-power AUP logic family, designed specifically for energy-constrained timing applications requiring high noise immunity, wide VCC operation, and integrated oscillator support.
FAQ
What is the function of the EN pin on the 74AUP1Z04GW/C125?
The EN pin on the 74AUP1Z04GW/C125 is an active-LOW enable input with Schmitt-trigger action. When driven HIGH, it places the device in low-power disable mode: X1 is pulled HIGH via internal RPU, X2 is set LOW, and Y is driven HIGH. This state reduces ICC to ≤75 µA and eliminates crystal oscillation while maintaining safe bias conditions. The Schmitt trigger ensures reliable switching even with slow-rising/falling control signals across the full 0.8–3.6 V VCC range.
How does the 74AUP1Z04GW/C125 support partial power-down in system designs?
The 74AUP1Z04GW/C125 supports partial power-down via its IOFF circuitry on output Y. When VCC = 0 V, the IOFF feature disables the Y output stage, limiting leakage current to ±0.75 µA maximum regardless of voltage applied to Y or other pins. This prevents damaging backflow current into the powered-down device from live system buses, enabling safe integration in multi-rail architectures where subsystems power up/down independently - a critical capability for automotive domain controllers and industrial safety PLCs.
What crystal load capacitance range is compatible with the 74AUP1Z04GW/C125?
The 74AUP1Z04GW/C125 is validated for use with crystals requiring load capacitances from 5 pF to 30 pF, as confirmed by dynamic characterization up to CL = 30 pF in the datasheet. Its low input capacitance (1.3 pF at X1) and stable Rbias (1.07–3.11 MΩ) allow precise tuning using standard series C1/C2 networks. Designers should calculate C1 and C2 per CL = (C1×C2)/(C1+C2) + Cs, where Cs = 1.5 pF (input capacitance of X2), to match the crystal manufacturer's specified CL value - ensuring reliable startup and frequency accuracy across −40 °C to +125 °C.
Does the 74AUP1Z04GW/C125 require external bias resistors for crystal operation?
No, the 74AUP1Z04GW/C125 does not require external bias resistors. It integrates both Rbias (1.07–3.11 MΩ) between X2 and GND to set the inverter's DC operating point near mid-supply, and RPU (pull-up) from X1 to VCC for disable-mode biasing. These internal resistors eliminate the need for discrete components typically used in Pierce oscillators, reducing BOM count by two parts, minimizing layout sensitivity, and improving long-term stability - especially under temperature variation where external resistor drift would degrade frequency accuracy.
What is the maximum operating frequency supported by the 74AUP1Z04GW/C125 in crystal oscillator applications?
The 74AUP1Z04GW/C125 is characterized for crystal oscillator operation up to 20 MHz, as validated by NXP's application documentation and dynamic testing across VCC = 0.8–3.6 V and Tamb = −40 °C to +125 °C. Its propagation delay (X1→X2) remains below 2.0 ns at 3.3 V with 5 pF load, supporting fundamental-mode crystals in that range. While higher frequencies may be achievable with overtone crystals or optimized layouts, the device's specified and tested performance envelope for stable, low-jitter oscillation is 32.768 kHz to 20 MHz - covering RTC, MCU clocks, and industrial communication timing.
74AUP1Z04GW/C125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 6-TSSOP, SC-88, SOT-363
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Inverter, X-Tal Driver
- Supply Voltage:
- 0.8V ~ 3.6V
- Number of Bits:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-363
74AUP1Z04GW/C125 FAQ
1.How can I place an order for 74AUP1Z04GW/C125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP1Z04GW/C125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP1Z04GW/C125 reliable?
The price and inventory of 74AUP1Z04GW/C125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP1Z04GW/C125 is usually 5 days.
3.What payment methods are accepted for 74AUP1Z04GW/C125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP1Z04GW/C125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP1Z04GW/C125?
74AUP1Z04GW/C125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP1Z04GW/C125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP1Z04GW/C125?
For technical support, including 74AUP1Z04GW/C125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP1Z04GW/C125 requirements.
6.How does Aetrix verify that 74AUP1Z04GW/C125 is sourced from the original manufacturer or authorized distributors?
All 74AUP1Z04GW/C125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP1Z04GW/C125 meets industry standards.
7.What is the process for return or replacement of 74AUP1Z04GW/C125?
All 74AUP1Z04GW/C125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP1Z04GW/C125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP1Z04GW/C125 part is unused and in its original packaging.
Return procedure for 74AUP1Z04GW/C125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP1Z04GW/C125 Tags
-
MC14490DWR2G
onsemi
-
SY58600UMG-TR
Microchip Technology
-
MC100EP16DTR2G
onsemi
-
MC100EP16MNR4G
onsemi
-
74LVC1GX04GW,125
Nexperia USA Inc.
-
CD4007UBE
Texas Instruments
-
NXS0104PWJ
Nexperia USA Inc.
-
CD74HC283M96
Texas Instruments
-
SN74LVC1GX04DCKR
Texas Instruments
-
SN74F283N
Texas Instruments
-
SN74LVC1404DCTR
Texas Instruments
-
SN74LVC1GX04DBVR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
