Nexperia USA Inc. 74AUP1Z125GN,132

Overview

74AUP1Z125GN,132 from Nexperia is a low-power crystal oscillator driver IC with integrated enable input, internal bias and pull-up resistors, and 3-state output. It operates across 0.8 V to 3.6 V supply, features Schmitt-trigger inputs for noise immunity, and delivers stable X1→X2/Y propagation delays as low as 0.3 ns (VCC = 3.6 V, CL = 5 pF). Used in ultra-low-power timing circuits for portable medical sensors and battery-powered IoT nodes.

For engineers reviewing the 74AUP1Z125GN,132 datasheet, 74AUP1Z125GN,132 pinout, 74AUP1Z125GN,132 application, or 74AUP1Z125GN,132 equivalent, key selection criteria include its 0.9 × 1.0 × 0.35 mm XSON6 package, 1.08–3.08 MΩ internal bias resistance, 75 μA max ICC at 125 °C, EN-active-Low 3-state control, and guaranteed operation from –40 °C to +125 °C.

Technical Context

The 74AUP1Z125GN implements a single-stage CMOS inverter-based Pierce oscillator driver with dual outputs: buffered Y (3-state) and unbuffered X2. Its internal R_bias (1.08–3.08 MΩ) sets mid-supply DC bias on X1, enabling linear-region amplification for reliable crystal startup. The EN input controls power-down mode by pulling X1 HIGH via internal R_PU, forcing X2 LOW and Y into high-impedance state.

Schmitt-trigger action on both EN and X1 inputs ensures robust operation across full V_CC range (0.8–3.6 V), tolerating slow edges up to 200 ns/V. Output drive strength scales with V_CC: VOH ≥ V_CC – 0.11 V (IO = –20 μA), VOL ≤ 0.50 V (IO = 4.0 mA, V_CC = 3.0 V), supporting direct interface with 1.2 V, 1.8 V, and 3.3 V logic systems.

Key Specifications

Pinout & Package

XSON6 package (SOT1115): extremely thin small outline, no leads, 6-terminal, 0.9 × 1.0 × 0.35 mm body. Pin 1 indicator located below marking code in lower-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar crystal driver applications.

Compared with 74AUP1Z125GN,132, the GM variant trades 0.45 mm width for improved thermal mass and solder joint visibility, while the GS variant offers identical thickness with standardized 1.0 mm square footprint-enabling layout reuse without compromising crystal drive performance or low-power operation.

Availability

74AUP1Z125GN,132 is available at Aetrix Electronics and suitable for wearable health monitors, automotive TPMS modules, industrial PLC I/O modules, and smart home Zigbee coordinators requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP1Z125GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable, and efficient discrete, logic, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP1Z125 belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family, engineered specifically for battery-critical and thermally demanding timing applications requiring sub-100 μA quiescent current and guaranteed operation to +125 °C.

FAQ

What is the function of the internal R_bias resistor?

The internal R_bias (1.08–3.08 MΩ) establishes a DC bias point near V_CC/2 at the X1 input, placing the inverter in its high-gain linear region. This ensures sufficient loop gain for reliable crystal startup and sustained oscillation without external bias components, directly supporting Pierce oscillator topology per Figure 11.

Can the 74AUP1Z125GN drive crystals above 10 MHz?

Yes-the 74AUP1Z125GN supports fundamental-mode crystals up to at least 24 MHz, as confirmed by typical forward transconductance (g_fs) of 32.4 mA/V at 3.6 V and propagation delay of 1.4 ns (CL = 5 pF). Designers must verify drive level compliance per crystal manufacturer specs and use appropriate series limiting resistor (R1 ≈ X_C1) to avoid overdrive damage.

How does the EN pin behave during power-up?

During power-up, EN must be held LOW (or actively driven) until V_CC stabilizes within specification (0.8–3.6 V). If EN floats HIGH before V_CC reaches minimum operating voltage, the device enters disable mode with X1 pulled HIGH and Y in high-impedance state-preventing unintended oscillation but requiring controlled reset sequencing for guaranteed startup.

Is external load capacitance required on the Y output?

No external load capacitance is required on Y for basic functionality, but CL impacts propagation delay and rise/fall times. Table 8 shows t_pd increases from 1.4 ns (CL = 5 pF) to 2.7 ns (CL = 30 pF) at 3.6 V. For clock distribution, keep CL ≤ 15 pF to maintain sub-2 ns delay; add series termination only if signal integrity analysis indicates overshoot.