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Nexperia USA Inc. 74AUP2G00GM,125
- Part No.:
- 74AUP2G00GM,125
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Gates and Inverters
- Package:
- 8-XFQFN Exposed Pad
- Datasheet:
-
74AUP2G00GM,125.pdf
- Description:
- IC GATE NAND 2CH 2-INP 8XQFN
- Quantity:
- Payment:
- Shipping:
Inventory:2,073
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Product details
Overview
74AUP2G00GM,125 from Nexperia is a low-power dual 2-input NAND gate IC with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering propagation delay as low as 1.0 ns at 3.3 V (CL = 5 pF), ICC ≤ 0.9 μA max, and IOFF-enabled partial power-down capability for system-level power gating in battery-powered sensor interfaces.
For engineers reviewing the 74AUP2G00GM,125 datasheet, 74AUP2G00GM,125 pinout, 74AUP2G00GM,125 application, or 74AUP2G00GM,125 equivalent, this device serves as a rail-to-rail compatible logic building block in ultra-low-power IoT node control paths, level-shifting I²C/SPI signal conditioning, and noise-immune reset synchronization where sub-1-μA static current and 0.8 V minimum VCC are critical.
Technical Context
This device implements two independent NAND gates with Schmitt-trigger input thresholds-VIH ≥ 0.65×VCC and VIL ≤ 0.35×VCC across 0.9–1.95 V VCC-enabling robust operation with slow-rising signals from RC networks or mechanical switches. Its IOFF circuit actively disables outputs during VCC = 0 V, preventing back-current flow into powered subsystems.
Designed for mixed-voltage systems, it accepts input voltages up to 3.6 V regardless of VCC (0.8–3.6 V), supports JEDEC standards JESD8-12 through JESD8-B, and maintains VOL ≤ 0.45 V at 4 mA sink while achieving VOH ≥ 2.3 V at 4 mA source under full temperature range (–40 °C to +125 °C).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 0.8 V to 3.6 V - enables direct interface with 0.9 V logic rails, 1.2 V microcontrollers, and 3.3 V peripherals without level shifters. |
| tpd (max) | 4.7 ns at VCC = 3.0–3.6 V, CL = 5 pF - ensures timing-critical combinational logic paths meet <5 ns budget in portable MCU peripheral gating. |
| ICC (max) | 0.9 μA at VCC = 0.8–3.6 V - reduces quiescent power in always-on wake-up circuits by >95% vs. standard AHC/AHCT logic. |
| IOFF Leakage | ±0.75 μA at VCC = 0 V - guarantees safe isolation when one domain powers down while others remain active in multi-rail SoM designs. |
| Input Thresholds | VIH ≥ 0.70×VCC / VIL ≤ 0.25×VCC (–40 °C to +125 °C) - provides ≥400 mV hysteresis margin for noisy industrial sensor inputs. |
| ESD Rating | HBM >5000 V, CDM >1000 V - eliminates need for external ESD protection in handheld medical and wearables PCB layouts. |
| Operating Temp | –40 °C to +125 °C - qualified for under-hood automotive body control modules and industrial motor drive logic supervision. |
Pinout & Package
XQFN8 (SOT902-2) plastic extremely thin quad flat no-lead package; 8 terminals; body 1.6 × 1.6 × 0.55 mm; wettable flanks; thermal pad exposed on underside.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1A | First NAND gate input - accepts 0–3.6 V signals independent of VCC; Schmitt-triggered for noise rejection. |
| 2 | 1B | First NAND gate input - identical electrical behavior to Pin 1; enables dual-input logic function per gate. |
| 3 | 1Y | First NAND gate output - drives capacitive loads up to 30 pF with guaranteed VOL/VOH across full VCC and temp range. |
| 4 | GND | Digital ground reference - must be connected to system ground plane; ties internal ESD structures and IOFF control. |
| 5 | 2Y | Second NAND gate output - electrically isolated from 1Y; supports independent fan-out to separate subsystems. |
| 6 | 2B | Second NAND gate input - shares same VIH/VIL specs and hysteresis as Pins 1 and 2. |
| 7 | 2A | Second NAND gate input - complements Pin 6 to form second 2-input NAND function. |
| 8 | VCC | Supply voltage input - powers both gates and IOFF circuitry; decoupling capacitor required within 3 mm. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Guarantees clean switching with slow edges (Δt/ΔV ≤ 200 ns/V), eliminating external hysteresis components in RC-debounced switch interfaces. |
| IOFF partial power-down | Disables outputs at VCC = 0 V, blocking back-current flow - essential for hot-swap I/O expansion and battery-isolated subsystems. |
| Rail-to-rail input tolerance | Accepts VI = 0–3.6 V regardless of VCC setting, enabling seamless interfacing between 1.2 V sensors and 3.3 V host processors. |
| Ultra-low ICC | 0.9 μA maximum supply current allows integration into nanoampere wake-up chains without compromising battery life. |
| JEDEC-compliant voltage ranges | Validated across five JEDEC sub-ranges (JESD8-12 to JESD8-B), ensuring interoperability with legacy and next-gen low-voltage ASICs. |
Applications
| Industrial Sensor Interface | IoT Edge Node Control |
|---|---|
|
Use Scenario: Debouncing mechanical limit switches in PLC I/O modules with long cable runs subject to EMI. IC Role / Device Role / Timing Role: Dual NAND configured as SR latch + Schmitt-trigger buffer; synchronizes asynchronous switch transitions to 10 kHz controller clock domain. Use Value: Eliminates external RC filters and Schmitt buffers, reducing BOM count by 3 components per channel while maintaining >400 mV noise margin. |
Use Scenario: Enabling/disabling BLE radio and environmental sensor power domains based on motion-detection interrupt. IC Role / Device Role / Timing Role: NAND gate implements AND-NOT logic to assert enable only when MCU GPIO is high AND motion flag is asserted. Use Value: Achieves <1 μA total standby current via IOFF isolation, extending coin-cell battery life to >2 years in maintenance-free deployments. |
| Automotive Body Control | Medical Wearable Power Sequencing |
|
Use Scenario: Validating door lock actuator feedback signals before engaging motor driver in 12 V vehicle architecture. IC Role / Device Role / Timing Role: NAND gate performs logical AND of two redundant Hall-effect sensor outputs to confirm closed position. Use Value: Operates reliably at 125 °C ambient and withstands load-dump transients due to 4.6 V absolute max VI rating. |
Use Scenario: Sequencing power to ECG analog front-end and digital processing unit in patch-style cardiac monitor. IC Role / Device Role / Timing Role: Dual NAND gates generate staggered enable pulses with precise 100 ns inter-stage delay using internal propagation characteristics. Use Value: Removes need for discrete RC timing networks, improving production yield and reducing board area by 2.1 mm² per sequencing path. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 2-input NAND gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G00DPWR | Higher ICC (10 μA typ), no Schmitt inputs, VCC min = 1.65 V, no IOFF. | Not suitable for sub-1-V systems or partial power-down; requires external hysteresis for noisy inputs. | Select only if operating exclusively at 1.8 V+ with clean signal sources and no power-gating requirements. |
| 74LVC2G00GW,125 | Same package (SOT363), but lacks Schmitt inputs and IOFF; ICC = 2 μA max; VCC min = 1.65 V. | Cannot replace in 0.8–1.65 V domains or hot-swap isolation scenarios; lower noise immunity. | Use only in cost-sensitive 1.8 V consumer applications where Schmitt and IOFF are non-critical. |
Compared with SN74LVC2G00DPWR and 74LVC2G00GW,125, the 74AUP2G00GM,125 uniquely delivers sub-1-μA static current, 0.8 V operation, Schmitt-trigger noise immunity, and IOFF isolation-making it the sole choice for ultra-low-power, mixed-voltage, and fail-safe power-domain boundary applications.
Availability
74AUP2G00GM,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, IoT edge node control, automotive body electronics, and medical wearable power sequencing requiring stable component supply across extended temperature and ultra-low-power constraints.
Supply support for 74AUP2G00GM,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions, with leadership in energy-efficient and space-constrained applications.
The 74AUP (Advanced Ultra-low-power) family targets battery-operated and thermally constrained systems requiring nanowatt static power, wide VCC flexibility, and robust signal integrity-designed specifically for next-generation IoT, automotive, and portable medical devices.
FAQ
Does 74AUP2G00GM,125 support true bidirectional level shifting?
No. While its inputs tolerate 0–3.6 V regardless of VCC, the outputs are unidirectional and referenced to VCC. It cannot pass signals from a lower-voltage domain to a higher-voltage domain without external pull-up resistors or dedicated level translators.
What is the thermal pad connection requirement for SOT902-2 package?
The exposed thermal pad (Pin 9, not numbered in 8-pin count) must be soldered to a dedicated PCB thermal land connected to GND. Failure to do so degrades thermal resistance by >40%, risking exceeding 125 °C junction temperature under sustained 20 mA output loading.
Can IOFF functionality be used with VCC = 0.3 V?
No. IOFF activates only when VCC ≤ 0.2 V. At VCC = 0.3 V, the device enters undefined state per datasheet Table 7 ΔIOFF specification; outputs may source unintended current. Full isolation requires VCC = 0 V.
Is propagation delay matched between the two NAND gates?
Yes. Matching is guaranteed within ±0.3 ns across –40 °C to +125 °C and 0.8–3.6 V VCC per datasheet Table 8, enabling use in differential clock conditioning or balanced logic paths without skew compensation.
74AUP2G00GM,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 8-XFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- NAND Gate
- Number of Circuits:
- 2
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Max):
- 500 nA
- Current - Output High, Low:
- 4mA, 4mA
- Input Logic Level - Low:
- 0.7V ~ 0.9V
- Input Logic Level - High:
- 1.6V ~ 2V
- Max Propagation Delay @ V, Max CL:
- 6.5ns @ 3.3V, 30pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XQFN (1.6x1.6)
74AUP2G00GM,125 FAQ
1.How can I place an order for 74AUP2G00GM,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G00GM,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G00GM,125 reliable?
The price and inventory of 74AUP2G00GM,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G00GM,125 is usually 5 days.
3.What payment methods are accepted for 74AUP2G00GM,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP2G00GM,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP2G00GM,125?
74AUP2G00GM,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP2G00GM,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G00GM,125?
For technical support, including 74AUP2G00GM,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G00GM,125 requirements.
6.How does Aetrix verify that 74AUP2G00GM,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G00GM,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G00GM,125 meets industry standards.
7.What is the process for return or replacement of 74AUP2G00GM,125?
All 74AUP2G00GM,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G00GM,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G00GM,125 part is unused and in its original packaging.
Return procedure for 74AUP2G00GM,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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