Nexperia USA Inc. 74AUP2G00GN,115

Overview

74AUP2G00GN,115 from Nexperia is a dual 2-input NAND gate logic IC operating from 0.8 V to 3.6 V supply, with typical propagation delay of 2.9 ns at 3.3 V and 30 pF load, static power dissipation below 1 µW, and designed for low-power portable and battery-operated applications including mobile interface control and sensor signal conditioning.

For engineers reviewing the 74AUP2G00GN,115 datasheet, 74AUP2G00GN,115 pinout, 74AUP2G00GN,115 application, or 74AUP2G00GN,115 equivalent, key selection criteria include supply voltage range compatibility, propagation delay vs. load capacitance, I_OFF leakage under power-down, output drive strength (±4 mA at V_CC = 3.3 V), and guaranteed operation down to 0.8 V for ultra-low-voltage system integration.

Technical Context

This device implements two independent CMOS NAND gates in a single die, each with rail-to-rail input voltage tolerance and overvoltage-tolerant inputs up to 3.6 V regardless of supply level. It uses advanced AUP (Advanced Ultra Low Power) process technology to achieve sub-1 µW static power consumption while maintaining full 3.3 V logic compatibility.

The logic function conforms to IEEE Std 1164 standard for 2-input NAND: Y = NOT(A AND B). Output stages are fully specified for driving capacitive loads up to 50 pF with monotonic edge response and no overshoot beyond ±0.3 V under defined test conditions.

Key Specifications

Pinout & Package

Supplied in a 6-pin XSON-6 (1.45 × 1.0 mm) package with 0.5 mm pitch, thermally enhanced for low-power logic density and PCB space efficiency.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual 2-input NAND gate applications.

Compared with SN74LVC2G00DBVR, 74AUP2G00GN,115 trades drive strength for 10× lower static power; compared with 74LVC2G00GM,132, it offers relaxed pitch for higher first-pass yield in standard SMT lines.

Availability

74AUP2G00GN,115 is available at Aetrix Electronics and suitable for mobile sensor interface, IoT edge node control, and wearable health monitor designs requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for 74AUP2G00GN,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential semiconductors, delivering high-performance, reliable components for automotive, industrial, and consumer applications.

The 74AUP series targets ultra-low-power logic in battery-constrained systems, emphasizing sub-1 µW static consumption, wide supply flexibility, and robust mixed-voltage interoperability.

FAQ

Is 74AUP2G00GN,115 compatible with 1.2 V core logic?

Yes. The device guarantees full functionality at V_CC = 1.2 V, including specified propagation delay, output drive, and input threshold levels per JEDEC JESD8-12E. Input hysteresis ensures noise immunity, and output VOH/VOL remain compliant across the entire 0.8–3.6 V range.

Can inputs be driven with 3.3 V signals while V_CC = 1.8 V?

Yes. Inputs are overvoltage tolerant up to 3.6 V regardless of V_CC level. This allows direct connection to 3.3 V peripherals without external level-shifting circuitry, reducing BOM count and PCB area in mixed-voltage systems.

What is the maximum capacitive load this device can drive reliably?

The device is characterized for loads up to 50 pF with monotonic edges and no overshoot beyond ±0.3 V. For loads exceeding 30 pF, propagation delay increases linearly-e.g., 4.1 ns at 50 pF and 3.3 V supply-while maintaining full logic integrity and timing margin.

Does this part support hot insertion or partial power-down?

Yes. With I_OFF leakage < ±100 nA and overvoltage-tolerant inputs, the device supports live insertion into powered backplanes and maintains isolation when V_CC = 0 V. No bus contention occurs, and inputs remain high-impedance without pull-up/pull-down requirements.