Nexperia USA Inc. 74AUP2G00GT,115

Overview

74AUP2G00GT,115 from Nexperia is a low-power dual 2-input NAND gate in an XSON8 package (SOT833-1), operating across 0.8 V to 3.6 V supply voltage with Schmitt-trigger inputs for noise immunity and IOFF circuitry enabling partial power-down mode. It delivers propagation delay as low as 1.0 ns at 3.6 V (CL = 5 pF) and static ICC ≤ 0.9 μA max, supporting space-constrained battery-powered logic interfacing in portable instrumentation and sensor signal conditioning.

For engineers reviewing the 74AUP2G00GT,115 datasheet, 74AUP2G00GT,115 pinout, 74AUP2G00GT,115 application, or 74AUP2G00GT,115 equivalent, key selection criteria include its ultra-low quiescent current, wide VCC range compatibility with 1.2 V/1.8 V/3.3 V domains, Schmitt-trigger input hysteresis for slow-edge tolerance, and IOFF-enabled isolation during system power sequencing.

Technical Context

This device implements two independent NAND gates with Schmitt-trigger inputs-each exhibiting hysteresis (VIH − VIL ≥ 0.3×VCC at 1.2 V–1.95 V) to reject noise on slow-rising/falling signals across its full 0.8 V–3.6 V operating range. Its IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current up to ±0.75 μA.

Dynamic performance is characterized by CL-dependent propagation delays: 1.0–4.7 ns over VCC = 3.0–3.6 V and CL = 5–30 pF, with CPD = 3.9 pF enabling precise dynamic power estimation (PD = CPD × VCC² × fi × N). Input capacitance is 0.8 pF; output capacitance is 1.7 pF.

Key Specifications

Pinout & Package

XSON8 plastic extremely thin small outline package (SOT833-1); no leads; 8 terminals; body dimensions 1.0 mm × 1.95 mm × 0.5 mm; thermal pad omitted; pin 1 index located at lower-left corner below marking code "p00".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual 2-input NAND gate applications.

Compared with SN74LVC2G00DPWR, the 74AUP2G00GT,115 offers 11× lower static current and essential Schmitt-trigger noise rejection, while its obsolescence-free status and tighter thermal profile (0.5 mm height vs. 0.65 mm) make it preferable for next-gen compact, battery-sensitive designs.

Availability

74AUP2G00GT,115 is available at Aetrix Electronics and suitable for industrial sensor interface, portable medical device logic, automotive body control modules, and IoT edge node signal routing requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for 74AUP2G00GT,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in high-volume applications.

The 74AUP (Advanced Ultra-low Power) logic family targets battery-operated and thermally constrained systems where nanowatt static power, wide VCC flexibility, and robust signal integrity are mandatory design requirements.

FAQ

Does 74AUP2G00GT,115 support mixed-voltage operation - e.g., 1.8 V inputs with 3.3 V VCC?

Yes. Inputs accept voltages up to 3.6 V regardless of VCC level, enabling direct connection of higher-voltage signals (e.g., 1.8 V or 2.5 V GPIOs) to a 3.3 V-powered device without external level shifters. This is explicitly specified in Table 6 (VI input voltage: 0–3.6 V).

What is the minimum VCC required for guaranteed logic functionality at −40 °C to +125 °C?

The minimum guaranteed VCC is 0.8 V across the full −40 °C to +125 °C range, per Table 6. At this voltage, VIH is 0.25×VCC (0.2 V min), VIL is 0.30×VCC (0.24 V max), and tpd remains within specification (≤13.5 ns at CL = 5 pF, VCC = 0.8 V).

How does the IOFF feature behave when VCC ramps down during power sequencing?

IOFF activates when VCC drops below ~0.2 V, limiting power-off leakage to ±0.75 μA (Table 7). Output impedance rises above 100 MΩ, effectively isolating the output node from back-current flow - critical when driving shared buses or unpowered downstream ICs during controlled shutdown.

Can 74AUP2G00GT,115 replace 74AUP2G00DC in existing VSSOP8 layouts?

No. The 74AUP2G00GT,115 uses XSON8 (SOT833-1; 1.0 × 1.95 mm), while the 74AUP2G00DC uses VSSOP8 (SOT765-1; 2.3 mm body width). Footprints are incompatible - pad pitch, terminal count orientation, and thermal pad presence differ. Redesign is required for migration.