Nexperia USA Inc. 74AUP2G02DC,125

Overview

74AUP2G02DC from Nexperia is a low-power dual 2-input NOR gate logic IC with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ICC ≤ 1.4 μA max at −40 °C to +125 °C, tPD = 0.8 ns (min) at VCC = 3.0–3.6 V/CL = 5 pF, and IOFF-enabled partial power-down protection. It serves as a noise-immune signal combiner in battery-powered sensor interfaces and portable MCU peripheral control.

For engineers reviewing the 74AUP2G02DC datasheet, 74AUP2G02DC pinout, 74AUP2G02DC application, or 74AUP2G02DC equivalent, this page delivers verified package mapping (VSSOP8/SOT765-1), confirmed Schmitt-trigger input thresholds, IOFF leakage specs (±0.75 μA), propagation delay vs. voltage/load data, and direct alternatives with documented functional alignment and pinout compatibility.

Technical Context

This device implements two independent NOR gates with hysteresis on all inputs-enabling robust operation with slow-rising signals in noisy environments. Each gate exhibits rail-to-rail output swing and supports mixed-voltage interfacing, as inputs tolerate up to 3.6 V regardless of VCC.

The IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V while maintaining VI/VO tolerance from 0 V to 3.6 V. Static power is minimized via optimized CMOS topology, achieving ICC ≤ 0.9 μA (typ) at 25 °C and ≤ 1.4 μA (max) over full temperature range.

Key Specifications

Pinout & Package

VSSOP8 plastic very thin shrink small outline package (SOT765-1); 8 leads; body width 2.3 mm; 0.5 mm lead pitch; exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual 2-input NOR gate applications.

Compared with SN74AUP2G02DSFR and 74LVC2G02GW,125, the 74AUP2G02DC provides guaranteed −40 °C to +125 °C operation in VSSOP8 - making it the sole choice for thermally demanding automotive and industrial deployments where package familiarity and thermal margin are critical.

Availability

74AUP2G02DC is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable MCU peripheral control, automotive body control modules, and IoT edge node power sequencing requiring stable component supply across extended temperature ranges.

Supply support for 74AUP2G02DC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra Low Power) product line targets ultra-low-power digital logic in battery-operated and thermally constrained systems, emphasizing sub-μA static current, wide-VCC operation, and robust IOFF functionality.

FAQ

Does the 74AUP2G02DC support true bidirectional signal routing?

No. The 74AUP2G02DC is a unidirectional logic gate with defined inputs (1A/1B/2A/2B) and outputs (1Y/2Y). It lacks bus-hold, direction-control, or tri-state capability. Its IOFF feature only disables outputs during power-down-it does not enable reverse signal flow or bus arbitration.

Can the 74AUP2G02DC drive a 50 pF load reliably at 3.3 V?

Yes, but with increased propagation delay: at VCC = 3.3 V and CL = 50 pF, tPD rises to ~12 ns (extrapolated from 30 pF data showing 8.5 ns max). Output drive strength remains within ±20 mA limits, and VOL stays ≤0.50 V. For timing-critical paths, limit CL to ≤15 pF or add a buffer stage.

Is the Schmitt-trigger hysteresis adjustable or fixed?

Fixed. The hysteresis threshold is internally set and non-adjustable-typically ≥10 % of VCC across the full 0.8–3.6 V supply range. No external components or configuration pins modify the trigger points; values are process-trimmed and specified in the VIH/VIL tables for each VCC tier.

What is the maximum allowable input voltage when VCC = 0 V?

Inputs tolerate −0.5 V to +4.6 V even when VCC = 0 V, per Absolute Maximum Ratings (Table 5). This allows safe "hot insertion" into live backplanes or connection to powered subsystems before main supply ramps-enabled by the IOFF circuit's isolation behavior and input clamp diodes rated for ±50 mA.