NXP Semiconductors 74AUP2G02GM,125

Overview

74AUP2G02GM,125 from Nexperia is a low-power dual 2-input NOR gate logic IC with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ≤0.9 μA max ICC at 25 °C, and supporting partial power-down via IOFF circuitry. It is used in battery-powered sensor interface and level-shifting circuits where noise immunity and ultra-low static power are critical.

For engineers reviewing the 74AUP2G02GM,125 datasheet, 74AUP2G02GM,125 pinout, 74AUP2G02GM,125 application, or 74AUP2G02GM,125 equivalent, key selection criteria include its 0.8–3.6 V wide VCC range, IOFF-enabled partial power-down capability, Schmitt-trigger input hysteresis for slow-edge tolerance, and guaranteed operation from –40 °C to +125 °C.

Technical Context

This device implements two independent 2-input NOR gates in a single 8-terminal XQFN package (SOT902-2), with each gate featuring Schmitt-trigger inputs that provide defined switching thresholds and immunity to input noise or slow rise/fall times. The IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current during partial system power-down.

It complies with JEDEC standards JESD8-12 through JESD8-B across five voltage bands and meets HBM ESD >5000 V and CDM >1000 V. Propagation delay ranges from 0.8 ns (VCC = 3.6 V, CL = 5 pF) to 34.2 ns (VCC = 0.8 V, CL = 30 pF), enabling flexible timing design in mixed-voltage systems.

Key Specifications

Pinout & Package

XQFN8 package (SOT902-2): plastic extremely thin quad flat no-lead, 1.4 × 1.2 × 0.45 mm body, wettable flank terminals, 0.5 mm pitch, exposed thermal pad.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual NOR gate applications.

Compared with SN74LVC2G02DPWR and 74AHC2G02GW,125, the 74AUP2G02GM,125 uniquely combines ultra-low ICC, Schmitt-trigger inputs, and IOFF-making it the only choice for energy-constrained, noise-prone, or partial-power-down systems requiring dual NOR functionality.

Availability

74AUP2G02GM,125 is available at Aetrix Electronics and suitable for industrial sensor interface, low-power wearable control, automotive body control modules, and IoT edge node power sequencing requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AUP2G02GM,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency-enhancing components including logic, discrete, and MOSFET devices, serving automotive, industrial, and consumer markets with high-volume, high-reliability solutions.

The 74AUP (Advanced Ultra-low Power) logic family targets battery-powered and energy-sensitive applications, emphasizing sub-1-μA static current, wide VCC operability, and robust IOFF behavior for modern mixed-signal system architectures.

FAQ

Does 74AUP2G02GM,125 support true bidirectional I/O or bus-hold functionality?

No. It is a unidirectional dual NOR gate with standard push-pull outputs and no bus-hold or auto-direction circuitry. Inputs are Schmitt-triggered but not configurable as outputs; outputs cannot be driven externally without risk of damage unless VCC is present and IOFF is inactive.

Can 74AUP2G02GM,125 be used with 0.8 V microcontroller I/O without level shifting?

Yes. Its VCC range starts at 0.8 V, and inputs tolerate up to 3.6 V independently. When powered at 0.8 V, VIH is guaranteed ≥0.56 V and VIL ≤0.20 V, matching typical 0.8 V logic thresholds - enabling direct connection to sub-1 V MCUs like ARM Cortex-M0+ in ultra-low-power modes.

What is the thermal performance of the SOT902-2 (XQFN8) package under continuous 20 mA output load?

At Tamb = 85 °C and IO = 20 mA per output, junction temperature rise is ≤12 °C above ambient (θJA ≈ 600 K/W for minimal pad exposure). Full thermal relief requires 200 mm² of 2-oz copper connected to EPAD; with optimized layout, ΔTJ ≤4.5 °C is achievable.

Is the IOFF feature activated automatically, or does it require external control?

IOFF activates automatically when VCC drops below ~0.2 V - no external enable signal or configuration is needed. The internal circuit detects VCC collapse and disables outputs within 100 ns, preventing backflow current regardless of input/output voltage states.