Nexperia USA Inc. 74AUP2G02GS,115

Overview

74AUP2G02GS,115 from Nexperia is a dual 2-input NOR gate logic IC with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ultra-low static ICC ≤ 1.4 μA (max at −40 °C to +125 °C), IOFF-enabled partial power-down protection, and propagation delay as low as 0.8 ns (VCC = 3.0–3.6 V, CL = 5 pF). It serves in voltage-level tolerant signal conditioning for battery-powered sensor interfaces and low-power microcontroller peripheral logic.

For engineers reviewing the 74AUP2G02GS,115 datasheet, 74AUP2G02GS,115 pinout, 74AUP2G02GS,115 application, or 74AUP2G02GS,115 equivalent, this device is selected for sub-1-V logic compatibility, I/O voltage tolerance up to 3.6 V, robust ESD immunity (HBM >5 kV), and validated operation over −40 °C to +125 °C industrial temperature range.

Technical Context

This device implements two independent 2-input NOR gates with Schmitt-trigger input thresholds-enabling noise-immune signal recovery from slow-rising or degraded waveforms. Each gate features symmetric VIH/VIL thresholds referenced to VCC (e.g., VIH ≥ 0.70VCC at 0.8 V supply), ensuring reliable switching across its full voltage range.

The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA max, making it suitable for hot-swap and multi-rail partial-power-down systems. Input capacitance is tightly controlled at 0.8 pF, and output capacitance at 1.7 pF-minimizing dynamic loading in high-speed, low-energy routing.

Key Specifications

Pinout & Package

XSON8 package (SOT1203): extremely thin small outline, no leads, 8-terminal surface-mount with 1.35 mm × 1.0 mm × 0.35 mm body and exposed thermal pad (not electrically connected). Pin 1 index located below marking code on lower-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual 2-input NOR gate applications.

Compared with SN74LVC2G02DPWR, the 74AUP2G02GS,115 delivers 90% lower static current and Schmitt-trigger noise immunity-critical for energy harvesting nodes. Against 74AUP2G02GN,115, the GS variant provides enhanced manufacturability via larger terminal pitch while maintaining identical logic behavior and thermal performance.

Availability

74AUP2G02GS,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, low-power microcontroller peripherals, hot-swappable module control, and multi-rail power sequencing requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AUP2G02GS,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies-delivering high-performance, reliable logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and energy-sensitive applications, emphasizing sub-1-V operation, nanoamp quiescent current, and robust IOFF functionality for modern multi-rail systems.

FAQ

Does 74AUP2G02GS,115 support true 0.8 V logic operation with guaranteed timing?

Yes. Propagation delay is specified down to 0.8 V supply (tpd ≤ 17.0 ns at CL = 5 pF, Tamb = 25 °C), and VIH/VIL thresholds scale with VCC (e.g., VIH ≥ 0.75VCC at −40 °C to +125 °C), enabling functional operation across the full 0.8–3.6 V range without performance degradation.

Can 74AUP2G02GS,115 safely interface a 3.6 V signal to a 0.8 V powered system?

Yes. Inputs tolerate up to +4.6 V (absolute max), and VIH is defined as low as 0.25VCC at 0.8 V supply (i.e., 0.2 V), meaning a 3.6 V input will reliably register as HIGH. Output VOH remains ≥ VCC − 0.11 V, ensuring valid HIGH levels for downstream 0.8 V receivers.

What is the thermal derating behavior of 74AUP2G02GS,115 in SOT1203 package?

Total power dissipation derates linearly at 3.6 mW/K above +81 °C ambient. At 125 °C, Ptot is reduced from 250 mW (at 81 °C) to 94.4 mW-calculated as 250 mW − (125 − 81) × 3.6 mW. This is documented in Table 5 footnote [2] for SOT1203.

Is the IOFF feature activated automatically, or does it require external control?

IOFF activates automatically when VCC drops to 0 V-no external enable signal or configuration is needed. The circuitry detects VCC = 0 V and disables outputs within nanoseconds, limiting back-current to ±0.75 μA regardless of input/output pin voltages (0–3.6 V).