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Diodes Incorporated 74AUP2G04DW-7

Part No.:
74AUP2G04DW-7
Manufacturer:
Diodes Incorporated
Category:
Gates and Inverters
Package:
6-TSSOP, SC-88, SOT-363
Datasheet:
Aetrix74AUP2G04DW-7.pdf
Description:
IC INVERTER 2CH 2-INP SOT363
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:9,296

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Product details

Overview

74AUP2G04DW-7 from Diodes Incorporated is a dual CMOS inverter in SOT363 package, operating from 0.8V to 3.6V supply, delivering ±4mA output drive at 3.0V, with IOFF-enabled partial power-down protection and 1.9ns typical propagation delay (VCC = 3.3V, CL = 5pF), deployed in battery-powered portable logic interfaces.

For engineers reviewing the 74AUP2G04DW-7 datasheet, 74AUP2G04DW-7 pinout, 74AUP2G04DW-7 application, or 74AUP2G04DW-7 equivalent, this page delivers verified electrical specs, SOT363 terminal mapping, low-power design context, and real-world use cases for portable electronics signal inversion.

Technical Context

This device implements two independent standard-inverting logic gates with push-pull outputs and Schmitt-trigger inputs (250mV typical hysteresis at VCC = 3.0V), enabling robust noise immunity for slow-rising signals. Its IOFF circuit actively disables outputs during power-down, preventing back-current flow between powered and unpowered rails.

The AUP family targets ultra-low static current (ICC < 0.9µA) and dynamic capacitance (CPD = 6.0pF at 3.3V), supporting operation across industrial temperature range (–40°C to +125°C) while maintaining input thresholds scalable with VCC (e.g., VIH = 0.80×VCC for 0.8–1.65V range).

Key Specifications

Parameter Value and Actual Design Meaning
Supply Voltage Range 0.8V to 3.6V - enables direct interface with modern low-voltage microcontrollers and battery-supplied systems.
Output Drive ±4mA at 3.0V - sufficient to drive multiple 74AUP inputs or small capacitive loads without external buffering.
Propagation Delay 1.9ns typical (VCC = 3.3V, CL = 5pF) - supports high-speed signal inversion in compact portable timing paths.
Static Supply Current ICC < 0.9µA - extends battery life in always-on or sleep-mode logic monitoring circuits.
IOFF Leakage ±0.6µA max (VI/VO = 0–3.6V) - ensures safe isolation when one side of a mixed-voltage bus is powered down.
Input Hysteresis 250mV typical at VCC = 3.0V - rejects noise on slow-switching control lines like reset or enable signals.
ESD Protection 2kV HBM, 1kV CDM - meets IEC 61000-4-2 level for handheld and peripheral applications.

Pinout & Package

SOT363 (2.0mm × 2.0mm × 1.1mm, 0.65mm lead pitch) surface-mount package with exposed thermal pad not connected internally; RoHS-compliant, lead-free construction.

Pin/Terminal Circuit Role Design Meaning
1A Inverter 1 Input Accepts logic-level signal; Schmitt-trigger input tolerates slow edges and noise.
GND Ground Reference Common return path for both inverters and IOFF circuitry; must be low-impedance.
2A Inverter 2 Input Independent input with identical Schmitt characteristics as Pin 1A.
2Y Inverter 2 Output Push-pull active-high/low output; sinks or sources up to ±4mA at 3.0V.
VCC Power Supply Single supply rail for both gates; IOFF activates automatically when VCC = 0V.
1Y Inverter 1 Output Electrically isolated from 2Y; supports independent loading and routing.

Key Features

Feature Design Value
Ultra-low ICC 0.5–0.9µA typical - reduces quiescent power in always-on sensor wake-up logic.
IOFF Partial Power-Down Active at VCC = 0V - prevents backfeeding between live and dormant subsystems in multi-rail designs.
Schmitt-Trigger Inputs 250mV hysteresis at 3.0V - eliminates chatter on mechanical switch debouncing or noisy analog comparator outputs.
Wide VCC Range 0.8–3.6V - interoperable with 1.2V, 1.8V, 2.5V, and 3.3V logic families without level shifters.
Low CPD 6.0pF at 3.3V - minimizes dynamic switching power in high-frequency clock or data inversion paths.

Applications

Mobile Device Power Sequencing USB Interface Signal Conditioning

Use Scenario: Inverting enable signals for LDOs and PMICs during boot-up and sleep transitions in smartphones and tablets.

IC Role / Device Role / Timing Role: Dual inverter provides synchronized active-low control for voltage rails, with IOFF preventing leakage during deep-sleep states.

Use Value: Eliminates need for discrete pull-down resistors and external isolation FETs, reducing BOM count and PCB area.

Use Scenario: Level-shifting and edge sharpening of USB suspend/resume handshake signals between host controller and peripheral ICs.

IC Role / Device Role / Timing Role: Inverts and cleans up slow-rising USB ID or VBUS detect signals using Schmitt-trigger inputs.

Use Value: Ensures reliable detection of cable insertion/removal events under varying load and temperature conditions.

Industrial Sensor Node Logic Wearable Health Monitor Signal Path

Use Scenario: Inverting interrupt outputs from environmental sensors (e.g., motion, temperature) before feeding into ultra-low-power MCU GPIOs.

IC Role / Device Role / Timing Role: Provides logic polarity correction and noise filtering via hysteresis, operating directly from coin-cell voltage.

Use Value: Enables direct 0.8V–1.8V sensor-to-MCU interfacing without voltage translation, preserving sub-µA system sleep current.

Use Scenario: Inverting ECG electrode bias control signals and LED driver enable lines in compact wearable patches.

IC Role / Device Role / Timing Role: Dual gate handles separate analog front-end and optical subsystem controls with independent timing margins.

Use Value: Reduces standby current by >90% versus standard 74HC logic, extending single-charge battery life beyond 7 days.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual inverter applications.

Alternative Part Technical Difference Application Difference Selection Advice
SN74LVC2G04DBVR Higher ICC (1µA typ), wider VCC (1.65–5.5V), no Schmitt inputs, no IOFF. Requires external pull-downs for power-down safety; unsuitable for sub-1.65V battery operation. Choose only if 5V tolerance or higher drive (±24mA) is required and power-down isolation is handled elsewhere.
74AHC2G04GW,125 Higher VCC min (2.0V), faster tPD (1.5ns @ 3.3V), no IOFF, no Schmitt inputs. Lacks hysteresis and power-down protection - requires clean, fast-rising inputs and full-rail power management. Select when speed is critical and system guarantees monotonic, noise-free input transitions above 2.0V.

Compared with SN74LVC2G04DBVR and 74AHC2G04GW,125, the 74AUP2G04DW-7 uniquely combines sub-1V operation, Schmitt noise immunity, and IOFF isolation - making it the only choice for energy-constrained, mixed-voltage, and mechanically noisy portable designs.

Availability

74AUP2G04DW-7 is available at Aetrix Electronics and suitable for mobile device power sequencing, USB interface conditioning, and wearable health monitor signal path applications requiring stable component supply across extended product lifecycles.

Supply support for 74AUP2G04DW-7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and logic solutions for power management, signal integrity, and connectivity applications.

The 74AUP2G04DW-7 belongs to the Advanced Ultra Low Power (AUP) logic family, engineered specifically for extended battery life and robust operation in portable consumer and IoT edge devices.

FAQ

What is the minimum supply voltage for guaranteed operation of the 74AUP2G04DW-7?

The device is fully specified from 0.8V to 3.6V. At 0.8V, it maintains functional logic behavior with tPD ≤19.2ns (CL = 5pF) and VIH/VIL thresholds scaled to 0.80×VCC. Below 0.8V, timing and noise margin degrade unpredictably per datasheet limits.

Does the 74AUP2G04DW-7 require external pull-up or pull-down resistors on unused inputs?

No external resistors are needed: unused inputs must be tied to VCC or GND per datasheet Note 8. The Schmitt-trigger inputs eliminate floating-state risk, and internal clamping diodes plus low II (<±0.5µA) prevent latch-up or excessive current draw.

Can the 74AUP2G04DW-7 safely interface between 1.8V and 3.3V domains?

Yes - its 0.8–3.6V VCC range and input thresholds referenced to VCC allow direct connection to 1.8V outputs (VIH = 1.44V min) and driving 3.3V-tolerant inputs (VOH = 2.6V min at 3.0V). No level shifter is required if both sides share the same VCC rail.

How does IOFF function when VCC is disconnected during system sleep?

When VCC drops to 0V, the IOFF circuit automatically disables both outputs, limiting leakage to ±0.6µA max. This prevents current backflow from live 3.3V or 1.8V buses into the unpowered device, protecting downstream components and preserving battery charge.

74AUP2G04DW-7 Specifications

Product attributes
Attribute value
Manufacturer:
Diodes Incorporated
Series:
74AUP
Package/Case:
6-TSSOP, SC-88, SOT-363
Packaging:
Tape & Reel (TR)
Product Status:
Active
Logic Type:
Inverter
Number of Circuits:
2
Number of Inputs:
2
Features:
-
Voltage - Supply:
0.8V ~ 3.6V
Current - Quiescent (Max):
500 nA
Current - Output High, Low:
4mA, 4mA
Input Logic Level - Low:
0.7V ~ 0.9V
Input Logic Level - High:
1.6V ~ 2V
Max Propagation Delay @ V, Max CL:
5.4ns @ 3.3V, 30pF
Operating Temperature:
-40°C ~ 125°C
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
SOT-363

74AUP2G04DW-7 FAQ

1.How can I place an order for 74AUP2G04DW-7 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP2G04DW-7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AUP2G04DW-7 reliable?

The price and inventory of 74AUP2G04DW-7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G04DW-7 is usually 5 days.

3.What payment methods are accepted for 74AUP2G04DW-7?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP2G04DW-7 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74AUP2G04DW-7?

74AUP2G04DW-7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74AUP2G04DW-7 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74AUP2G04DW-7?

For technical support, including 74AUP2G04DW-7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G04DW-7 requirements.

6.How does Aetrix verify that 74AUP2G04DW-7 is sourced from the original manufacturer or authorized distributors?

All 74AUP2G04DW-7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G04DW-7 meets industry standards.

7.What is the process for return or replacement of 74AUP2G04DW-7?

All 74AUP2G04DW-7 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G04DW-7, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP2G04DW-7 part is unused and in its original packaging.

Return procedure for 74AUP2G04DW-7:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

74AUP2G04DW-7 Tags

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