Diodes Incorporated 74AUP2G04FW3-7

Overview

74AUP2G04FW3-7 from Diodes Incorporated is a dual CMOS inverter IC in the Advanced Ultra Low Power (AUP) logic family, designed for battery-powered portable systems requiring operation across 0.8V–3.6V supply rails. It delivers ±4mA output drive at 3.0V, features IOFF partial power-down protection, and integrates Schmitt-trigger inputs with ~250mV hysteresis at VCC = 3.0V for robust noise immunity in low-slew-rate signal paths-used in voltage-level translation and signal conditioning within notebook I/O subsystems.

For engineers reviewing the 74AUP2G04FW3-7 datasheet, 74AUP2G04FW3-7 pinout, 74AUP2G04FW3-7 application, or 74AUP2G04FW3-7 equivalent, this page provides verified package mapping (X2-DFN0910-6), confirmed dual-inverter Boolean function (Y = A̅), validated IOFF leakage specs (<±0.6µA), and real-world timing data (tpd = 1.5ns typ @ 3.3V, CL = 5pF) to support low-voltage logic interface design and BOM optimization.

Technical Context

This device implements two independent inverters with push-pull outputs and Schmitt-trigger inputs-enabling reliable signal regeneration of slow-rising or noisy digital signals. Its IOFF circuit actively disables outputs during power-down, preventing back-current flow when VCC = 0V while inputs remain biased.

The AUP family targets ultra-low static and dynamic power: ICC < 0.9µA (max) and CPD = 4pF (typ @ 3.6V), enabling integration into always-on sensor nodes and sleep-mode peripherals without compromising timing integrity across –40°C to +125°C operating range.

Key Specifications

Pinout & Package

X2-DFN0910-6 is a 0.9mm × 1.0mm × 0.35mm leadless surface-mount package with 0.35mm pad pitch and exposed thermal pad (not electrically connected). It complies with JESD30E and supports automated optical inspection and reflow soldering per IPC-7095.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual inverter applications.

Compared with SN74LVC2G04DBVR and 74AHC2G04GW,125, the 74AUP2G04FW3-7 uniquely combines sub-1V operation, IOFF, and Schmitt inputs-making it the only option for battery-constrained, mixed-slew-rate, and partial-power-down designs requiring guaranteed noise immunity and zero-backflow safety.

Availability

74AUP2G04FW3-7 is available at Aetrix Electronics and suitable for USB OTG adapters, wearable sensor hubs, smartphone display subsystems, and industrial PLC input stages requiring stable component supply across extended product lifecycles.

Supply support for 74AUP2G04FW3-7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and logic devices for power management, signal integrity, and connectivity applications.

The 74AUP2G04FW3-7 belongs to the Advanced Ultra Low Power (AUP) logic family, engineered specifically for extended battery life and robust operation in portable consumer electronics with aggressive voltage scaling and dynamic power management.

FAQ

What is the maximum recommended load capacitance for 74AUP2G04FW3-7 at 3.3V?

The datasheet specifies switching characteristics up to CL = 30pF, with tpd = 5.4ns (max) at 3.3V. Driving >30pF increases propagation delay nonlinearly and may exceed output drive capability-designs requiring >30pF loads should add series termination or buffer stages to maintain timing integrity and avoid excessive output current stress.

Does 74AUP2G04FW3-7 support true bidirectional signal translation?

No-it is a unidirectional inverter with fixed input/output roles (1A→1Y, 2A→2Y). While it can translate voltage levels across its 0.8V–3.6V range, it lacks bus-hold or direction-control logic. For bidirectional level shifting, dedicated translators like TXB0104 or PCA9306 are required.

Can unused inputs be left floating?

No. Per datasheet Note 8, all unused inputs must be tied to VCC or GND to prevent increased ICC, oscillation, or ESD susceptibility. Floating inputs cause undefined logic states and elevated static current due to internal MOSFET threshold uncertainty-this violates recommended operating conditions and risks system instability.

Is the X2-DFN0910-6 package thermally enhanced?

The package has an exposed thermal pad (per AP02002 layout guidelines), but it is not internally connected to any die node. Thermal performance relies solely on PCB copper area under the pad; no electrical connection exists, so grounding or leaving it floating yields identical thermal resistance-designers should maximize solder mask-defined copper area for optimal θJA reduction.