Nexperia USA Inc. 74AUP2G04GS,132

Overview

74AUP2G04GS,132 from Nexperia is a dual Schmitt-trigger inverter IC designed for ultra-low-power logic level inversion in space-constrained, battery-powered, and mixed-voltage digital systems. It operates across 0.8 V to 3.6 V supply, delivers ≤1.4 μA max ICC at −40 °C to +125 °C, features IOFF partial power-down protection, and supports rail-to-rail input tolerance up to 3.6 V - enabling use in I²C bus buffering, sensor interface signal conditioning, and low-noise microcontroller GPIO expansion.

For engineers reviewing the 74AUP2G04GS,132 datasheet, 74AUP2G04GS,132 pinout, 74AUP2G04GS,132 application, or 74AUP2G04GS,132 equivalent, this device is selected when sub-μA static current, wide-VCC compatibility, robust noise immunity (Schmitt inputs), and guaranteed IOFF behavior during partial system shutdown are required - not for high-speed clock distribution or analog switching.

Technical Context

The 74AUP2G04GS,132 implements two independent inverting buffers with hysteresis on each input, enabling reliable operation with slow-rising or noisy signals. Its IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current between powered and unpowered domains - critical for hot-swap and multi-rail power sequencing.

It uses advanced AUP (Advanced Ultra Low Power) CMOS process technology to achieve <1.4 μA max ICC across full temperature range while maintaining propagation delays as low as 1.0 ns (VCC = 3.0–3.6 V, CL = 5 pF) and output drive capability of ±4 mA at 3.0 V.

Key Specifications

Pinout & Package

XSON6 package (SOT1202): extremely thin small outline, no leads, 1.0 mm × 1.0 mm × 0.35 mm body, 6-terminal surface-mount design optimized for high-density PCB layouts and thermal performance in compact enclosures.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual inverter applications.

Compared with 74LVC2G04GW,125, the 74AUP2G04GS,132 delivers 3.5× lower static current and robust noise immunity, while SN74AUP2G04DSFR offers identical logic performance in a marginally smaller footprint - making the GS variant optimal for cost-sensitive, thermally unconstrained high-volume designs.

Availability

74AUP2G04GS,132 is available at Aetrix Electronics and suitable for industrial sensor interface, I²C bus translation, microcontroller GPIO expansion, and low-power display backlight control requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP2G04GS,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP2G04GS,132 belongs to Nexperia's Advanced Ultra Low Power (AUP) logic family, engineered specifically for energy-constrained, space-limited applications demanding sub-microwatt operation and robust mixed-voltage interoperability.

FAQ

Can 74AUP2G04GS,132 operate with VCC = 0.8 V while accepting 3.6 V input signals?

Yes. The device guarantees input voltage tolerance up to 3.6 V independent of VCC, per datasheet Table 3 and Section 2. This enables safe interfacing with higher-voltage peripherals without clamping diodes or external protection - provided input current remains within ±20 μA limits specified in Table 5.

Does the IOFF feature require external circuitry to activate?

No. IOFF activates automatically when VCC drops to 0 V; no enable pin, control signal, or external components are needed. The internal circuitry disables both outputs to high-impedance state, preventing back-current flow - verified in Table 7 (IOFF leakage ≤ ±0.75 μA at VCC = 0 V).

What is the maximum capacitive load the outputs can drive reliably?

The outputs are characterized up to 30 pF load capacitance (Table 8), with propagation delay increasing predictably (e.g., 2.6–6.9 ns at VCC = 3.0–3.6 V). For loads >30 pF, timing margins degrade; external buffer stages are recommended beyond 50 pF to maintain signal integrity and meet setup/hold requirements.

How does Schmitt-trigger action improve noise immunity compared to standard CMOS inverters?

Schmitt inputs provide hysteresis - typically ≥0.1×VCC - meaning the rising and falling input thresholds differ. This prevents multiple output toggles when input voltage lingers near the switching point due to noise or slow edges, ensuring single, clean transitions even with >100 ns input rise/fall times (Δt/ΔV ≤ 200 ns/V per Table 6).