Nexperia USA Inc. 74AUP2G04GW,125

Overview

74AUP2G04GW,125 from Nexperia is a dual CMOS inverter with Schmitt-trigger inputs, designed for low-voltage logic level translation and signal conditioning in battery-powered and space-constrained systems. It operates across 0.8 V to 3.6 V supply, delivers ≤1.4 μA max ICC at −40 °C to +125 °C, features IOFF partial power-down protection, and supports 5–30 pF load capacitance with propagation delays as low as 1.0 ns at 3.3 V. It is used in portable sensor interfaces and I²C bus signal shaping.

For engineers reviewing the 74AUP2G04GW,125 datasheet, 74AUP2G04GW,125 pinout, 74AUP2G04GW,125 application, or 74AUP2G04GW,125 equivalent, this page provides verified functional identity, TSSOP6 package mapping, Schmitt-trigger input behavior, IOFF-enabled power-gating capability, and real-world timing performance under varying VCC and temperature conditions - all critical for ultra-low-power digital interface design.

Technical Context

The 74AUP2G04GW,125 implements two independent inverting buffers with hysteresis on each input, enabling robust noise immunity against slow-rising signals in mixed-signal environments. Its IOFF circuit actively disables outputs when VCC = 0 V, preventing backflow current during partial system shutdown.

It complies with JEDEC standards JESD8-12 through JESD8-B across five voltage bands and meets HBM ESD >5000 V and CDM >1000 V. The device is characterized from −40 °C to +125 °C and supports dynamic operation up to 100 MHz (with CL = 5 pF, VCC = 3.3 V).

Key Specifications

Pinout & Package

TSSOP6 (SOT363-2) plastic thin shrink small outline package: 6-pin, 1.25 mm body width, 0.65 mm pitch, exposed pad not present, RoHS-compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual inverter applications.

Compared with SN74LVC2G04DBVR and 74LVC2G14GW,125, the 74AUP2G04GW,125 uniquely balances sub-microamp static current, Schmitt-trigger robustness, and 0.8 V operability - making it optimal for energy-harvesting and coin-cell-powered edge devices where every nanoamp and millivolt matters.

Availability

74AUP2G04GW,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical device logic, I²C bus signal shaping, and low-power MCU wake-up circuits requiring stable component supply across extended temperature ranges.

Supply support for 74AUP2G04GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-performance, energy-efficient logic, analog, and discrete components for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and thermally constrained applications, delivering best-in-class static/dynamic power trade-offs without sacrificing speed or noise immunity.

FAQ

Does the 74AUP2G04GW,125 support true 0.8 V logic operation with guaranteed timing?

Yes. At VCC = 0.8 V and Tamb = −40 °C to +125 °C, the device guarantees tpd ≤ 12.6 ns (CL = 5 pF) and VIH/VIL thresholds scaled to 0.75×VCC and 0.25×VCC respectively - enabling interoperability with sub-1 V ASICs and energy-harvesting PMUs.

Can the IOFF feature be used to isolate powered-down sections in a multi-rail system?

Yes. When VCC = 0 V, IOFF disables both outputs regardless of input states, limiting leakage to ±0.75 μA. This enables safe bidirectional isolation between live 3.3 V domains and unpowered 1.2 V subsystems without external MOSFET switches.

What is the maximum capacitive load the 74AUP2G04GW,125 can drive while maintaining timing specs?

The device is fully characterized up to CL = 30 pF across all VCC and temperature ranges. At VCC = 3.3 V and +125 °C, tpd remains ≤ 6.9 ns (CL = 30 pF), confirming robust drive capability for PCB traces, connectors, and multiple gate inputs without added buffering.

How does the Schmitt-trigger input threshold vary with supply voltage?

VIH and VIL scale linearly: VIH = 0.70×VCC (min) at 0.8 V, rising to 2.0 V (min) at 3.0–3.6 V; VIL = 0.25×VCC (max) at 0.8 V, rising to 0.9 V (max) at 3.0–3.6 V. Hysteresis width is typically 0.2×VCC, ensuring consistent noise margin across the full operating range.