Nexperia USA Inc. 74AUP2G04GW-Q100H

Overview

74AUP2G04GW-Q100 from Nexperia is an automotive-grade dual CMOS inverter with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ultra-low static current (≤1.4 μA at +125 °C), IOFF-enabled partial power-down protection, and AEC-Q100 Grade 1 qualification for under-hood automotive control logic.

For engineers reviewing the 74AUP2G04GW-Q100 datasheet, 74AUP2G04GW-Q100 pinout, 74AUP2G04GW-Q100 application, or 74AUP2G04GW-Q100 equivalent, this device supports low-voltage signal inversion in battery-supplied modules, ECU input conditioning, and mixed-voltage interface buffering where rail tolerance, noise immunity, and power-down isolation are critical.

Technical Context

This dual inverter implements two independent Schmitt-trigger input stages driving complementary CMOS outputs, enabling robust signal restoration of slow-rising or noisy digital signals without external hysteresis components. Each channel operates with identical logic behavior and electrical specifications across the full temperature range (−40 °C to +125 °C).

The IOFF circuit actively disables both outputs when VCC = 0 V, blocking backflow current up to ±0.75 μA (max) and supporting hot-insertion and multi-rail partial power-down architectures. Input voltage tolerance extends to 3.6 V regardless of VCC level, allowing level-shifting between disparate supply domains.

Key Specifications

Pinout & Package

TSSOP6 (SOT363-2) package: plastic thin shrink small outline, 6-pin, 1.25 mm body width, 0.65 mm pitch, lead-free and RoHS compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual inverter applications.

Compared with SN74LVC2G04QPWRQ1 and 74AHC2G04-Q100, the 74AUP2G04GW-Q100 uniquely balances ultra-low ICC (<1.4 μA), Schmitt noise rejection, and AEC-Q100 Grade 1 compliance-making it optimal for always-on, space-constrained automotive subsystems where battery longevity and signal integrity are co-prioritized.

Availability

74AUP2G04GW-Q100 is available at Aetrix Electronics and suitable for automotive body control modules, infotainment power sequencing, engine sensor interfaces, and ADAS camera reset logic requiring stable component supply across extended temperature and long lifecycle programs.

Supply support for 74AUP2G04GW-Q100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency-enhancing components, with leadership in logic, discrete, and MOSFET technologies for automotive, industrial, and mobile markets.

The 74AUP (Advanced Ultra-low Power) logic family targets automotive and portable applications demanding nanowatt static power, wide supply flexibility, and robust signal integrity-designed specifically for battery-sensitive and thermally constrained electronic control units.

FAQ

Does the 74AUP2G04GW-Q100 support true bidirectional I/O?

No. It is a unidirectional dual inverter with dedicated inputs (1A, 2A) and outputs (1Y, 2Y). Neither input nor output terminals are configurable as bidirectional ports. The IOFF feature only disables output drivers during power-down-it does not enable bus-sharing or data direction control.

Can 74AUP2G04GW-Q100 drive a 50 pF capacitive load reliably?

Yes, but with increased propagation delay: at VCC = 3.3 V, tpd rises from 4.2 ns (CL = 15 pF) to approximately 6.9 ns (CL = 30 pF); extrapolation suggests ~8.5 ns at 50 pF. Output drive strength (±4 mA) remains sufficient, though rise/fall times will lengthen-verify timing margins in your specific layout and trace impedance.

What is the maximum input frequency supported for continuous toggling?

Based on tpd = 4.2 ns (typ) and minimum pulse width constraints, the device supports reliable operation up to ~100 MHz for symmetrical square waves. However, dynamic power (PD = CPD × VCC² × fi × N) must be monitored: at 3.3 V and 100 MHz, PD ≈ 440 μW per inverter-well within the 250 mW Ptot limit, but thermal design should account for cumulative die heating in dense layouts.

Is pin 1 marking visible under standard optical inspection?

Yes. Per datasheet Table 2, the marking code "p4" is laser-etched on the top surface, and the pin 1 indicator is a molded notch or dimple located on the lower left corner of the TSSOP6 body, directly below the marking-visible under 10× magnification and compatible with automated optical inspection (AOI) systems used in SMT line verification.