Nexperia USA Inc. 74AUP2G0604GFH

Overview

74AUP2G0604 from Nexperia is a dual-function low-power logic IC integrating one inverting buffer with open-drain output (1A→1Y) and one standard inverter (2A→2Y), operating across 0.8 V–3.6 V supply. It features Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and guaranteed operation from –40 °C to +125 °C - deployed in voltage-level translation, I²C bus buffering, and mixed-voltage interface isolation.

For engineers reviewing the 74AUP2G0604 datasheet, 74AUP2G0604 pinout, 74AUP2G0604 application, or 74AUP2G0604 equivalent, key selection criteria include open-drain vs. push-pull output behavior, sub-1 μA ICC max at 125 °C, IOFF-enabled backflow prevention during partial power-down, and validated 6-pin TSSOP6/XSON6 package compatibility with high-density PCB layouts.

Technical Context

This device implements two independent logic paths on a single die: the 1A-to-1Y path delivers open-drain inversion with programmable pull-up external to the IC, while the 2A-to-2Y path provides standard CMOS push-pull inversion. Both inputs incorporate Schmitt-trigger thresholds (VIH/VIL varying with VCC), enabling robust operation with slow-rising signals across the full 0.8–3.6 V range.

IOFF circuitry actively disables both outputs when VCC = 0 V, limiting leakage to ±0.75 μA and preventing current backflow into powered subsystems - critical for hot-swap and multi-rail power sequencing. Propagation delays are load- and voltage-dependent, ranging from 0.8 ns (VCC = 3.3 V, CL = 5 pF) to 21.1 ns (VCC = 0.8 V, CL = 15 pF).

Key Specifications

Pinout & Package

Available in TSSOP6 (SOT363-2) and multiple XSON6 variants (SOT886/SOT1115/SOT1202); all are 6-terminal, leadless or gull-wing packages rated for –40 °C to +125 °C operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output inverting buffer applications.

Compared with SN74LVC2G06DSFR and 74LVC2G14GW, the 74AUP2G0604 uniquely combines open-drain and push-pull inversion with IOFF and sub-1 μA quiescent current - making it the sole option for energy-constrained, multi-supply systems requiring bus isolation and glitch-immune signal conditioning.

Availability

74AUP2G0604 is available at Aetrix Electronics and suitable for industrial sensor interfaces, I²C bus extension, hot-swappable module control, and low-power wearable power sequencing requiring stable component supply across extended temperature ranges.

Supply support for 74AUP2G0604 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies - delivering high-performance, reliable logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) product line targets battery-powered and energy-sensitive applications, emphasizing nanowatt static power, wide-VCC operation, and robustness in harsh thermal and electrical environments.

FAQ

Can 74AUP2G0604 drive a 10 kΩ pull-up resistor on 1Y at 3.3 V?

Yes - with VOL ≤ 0.45 V at IO = 4 mA, the 1Y output can sink ≥330 μA while maintaining a valid LOW level. A 10 kΩ pull-up at 3.3 V draws only 330 μA, well within the 20 mA absolute maximum rating and consistent with I²C standard-mode drive capability.

Does the IOFF feature activate automatically when VCC drops below a threshold?

Yes - IOFF engages when VCC falls to 0 V (or near-zero), disabling both outputs regardless of input states. The datasheet specifies IOFF leakage remains ≤±0.75 μA at VCC = 0 V, and no external enable signal or biasing is required for this function.

What is the maximum capacitive load 2Y can drive while maintaining 4.3 ns tPD at 3.3 V?

At VCC = 3.3 V and CL = 5 pF, tPD is specified as 0.8–4.3 ns. Increasing load to 10 pF raises tPD to 1.2–5.4 ns. To maintain ≤4.3 ns, CL must stay at or below 5 pF - achievable with short PCB traces and minimal stubs in high-speed control paths.

Is the Schmitt-trigger hysteresis voltage fixed or VCC-dependent?

Hysteresis is VCC-dependent: VIH − VIL ≈ 0.3×VCC at 0.8–1.95 V, widening to ~1.1 V at 3.3 V. This scaling ensures consistent noise margin across supply voltages - e.g., ~300 mV at 1.0 V and ~1.1 V at 3.3 V - critical for reliable operation in variable-voltage systems.