Nexperia USA Inc. 74AUP2G0604GNH

Overview

74AUP2G0604 from Nexperia is a dual-function low-power logic IC containing one inverting buffer with open-drain output (1A→1Y) and one standard inverter (2A→2Y), operating across 0.8 V to 3.6 V supply. It features Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and dual outputs optimized for level-shifting and wired-OR bus interfacing in portable and battery-powered systems.

For engineers reviewing the 74AUP2G0604 datasheet, 74AUP2G0604 pinout, 74AUP2G0604 application, or 74AUP2G0604 equivalent, this device supports mixed-voltage signal translation, I²C-compatible open-drain communication, and low-quiescent-current control logic where static power below 1.4 μA and input tolerance up to 3.6 V are critical design requirements.

Technical Context

The 74AUP2G0604 integrates two independent logic functions in a single 6-pin XSON package: a Schmitt-triggered inverter driving a push-pull output (2Y), and an inverting buffer driving an open-drain output (1Y) capable of external pull-up to higher voltages. Both inputs accept 0–3.6 V regardless of VCC, enabling robust level translation.

Its IOFF circuit actively disables both outputs when VCC = 0 V, limiting backflow current to ±0.75 μA over –40 °C to +125 °C, while propagation delay remains ≤4.3 ns at VCC = 3.3 V with 5 pF load - ensuring timing predictability in high-speed, low-power control paths.

Key Specifications

Pinout & Package

XSON6 package (SOT1115): 0.9 mm × 1.0 mm × 0.35 mm body, no leads, 6-terminal land-grid array with pin 1 indicator in lower-left corner beneath marking code 'a6'.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output logic buffer applications.

Compared with NXP 74AUP2G0604GM, the GNH variant offers smaller footprint and better thermal resistance; versus TC7SZU04F, it delivers dual functionality, Schmitt inputs, and true open-drain capability - making GNH the sole choice for mixed-signal interface and low-power system control.

Availability

74AUP2G0604GNH is available at Aetrix Electronics and suitable for I²C level translation, low-power sensor conditioning, hot-swap module control, and battery-operated display enable applications requiring stable component supply across automotive-grade temperature ranges.

Supply support for 74AUP2G0604GNH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and discrete devices, with leadership in advanced packaging and automotive-qualified components.

The 74AUP (Advanced Ultra Low Power) product line targets battery-constrained and thermally sensitive applications - delivering nanowatt static power, wide-VCC operation, and robust IO architecture for next-generation portable and industrial electronics.

FAQ

Can 74AUP2G0604GNH drive a 10 kΩ pull-up resistor on 1Y at 3.3 V?

Yes. With 20 mA sink capability and VOL ≤ 0.5 V at 4 mA, the 1Y output easily pulls down a 10 kΩ pull-up to ≤0.33 V at 3.3 V - well within logic-low thresholds for 3.3 V CMOS receivers. Derating is unnecessary for this load.

Does the IOFF feature activate automatically when VCC drops below a threshold?

Yes. IOFF engages when VCC falls below approximately 0.2 V, disabling both outputs and limiting leakage to ±0.75 μA. No external control signal is required - the circuitry is fully integrated and self-activating during power collapse.

Is the 74AUP2G0604GNH pin-compatible with other 6-pin AUP-series buffers?

No. While functionally similar to 74AUP2G06 and 74AUP2G125, the GNH has unique pinout: 1A-GND-2A-2Y-VCC-1Y. Substituting requires PCB redesign - especially critical for GND and VCC placement affecting noise and thermal performance.

What is the maximum recommended capacitive load on 2Y for stable operation at 3.3 V?

The datasheet specifies guaranteed timing up to 30 pF. For reliable edge integrity and minimal overshoot (<10% VCC), keep total load (including trace capacitance) ≤20 pF. Above 30 pF, propagation delay increases nonlinearly and VOH degrades under heavy capacitive switching.