Nexperia USA Inc. 74AUP2G0604GWH

Overview

74AUP2G0604 from Nexperia is a dual-function low-power logic IC containing one inverting buffer with open-drain output (1A→1Y) and one standard inverter (2A→2Y), operating across 0.8 V to 3.6 V supply. It features Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and dual outputs optimized for level-shifting and wired-OR bus interfacing in battery-powered IoT sensor nodes.

For engineers reviewing the 74AUP2G0604 datasheet, 74AUP2G0604 pinout, 74AUP2G0604 application, or 74AUP2G0604 equivalent, this device supports ultra-low static current (≤1.4 μA), wide-VCC compatibility, and robust ESD tolerance (HBM >5 kV), making it critical for space-constrained, multi-rail voltage translation designs requiring guaranteed input hysteresis and power-gating safety.

Technical Context

The 74AUP2G0604 integrates two independent logic functions in one 6-pin package: a Schmitt-triggered inverter driving a push-pull output (2Y), and a Schmitt-triggered inverting buffer driving an open-drain output (1Y). Both inputs tolerate up to 3.6 V regardless of VCC, enabling mixed-voltage signal conditioning.

Its IOFF circuit actively disables both outputs when VCC = 0 V, limiting backflow current to ±0.75 μA - a key requirement for hot-swap and partial-power-down systems. Propagation delay ranges from 0.8 ns (VCC = 3.6 V, CL = 5 pF) to 21.1 ns (VCC = 0.8 V, CL = 30 pF), with consistent tPLH/tPHL symmetry across temperature (−40 °C to +125 °C).

Key Specifications

Pinout & Package

TSSOP6 (SOT363-2) package: plastic thin shrink small outline, 6 leads, 1.25 mm body width, lead pitch 0.65 mm. Pin 1 index located below marking code in lower-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output logic buffer applications.

Compared with SN74LVC2G06DSFR and 74LVC2G14GW, the 74AUP2G0604 uniquely combines open-drain and push-pull outputs with sub-μA static current and 0.8 V operation - making it irreplaceable for mixed-voltage, low-power, and bus-arbitration-sensitive designs.

Availability

74AUP2G0604 is available at Aetrix Electronics and suitable for industrial sensor interfaces, low-power I²C bus extenders, hot-swappable module detection, and programmable logic input conditioning requiring stable component supply across extended temperature and multi-rail voltage environments.

Supply support for 74AUP2G0604 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-performance logic, analog, and discrete components, with leadership in energy-efficient and reliable solutions for automotive, industrial, and mobile markets.

The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and thermally constrained applications where nanowatt static power, wide-VCC flexibility, and robust IO behavior are mandatory design requirements.

FAQ

Can 74AUP2G0604 drive a 10 kΩ pull-up resistor on 1Y while operating at 0.8 V VCC?

Yes. At VCC = 0.8 V, 1Y sinks ≤0.1 V at 20 μA load (per Table 8), resulting in <1 mV drop across 10 kΩ - well within logic LOW threshold. The device maintains valid VOL even at minimum supply, enabling ultra-low-voltage bus interfacing without compromising noise margin.

Does the IOFF feature disable both 1Y and 2Y simultaneously when VCC = 0 V?

Yes. The IOFF circuitry disables both outputs regardless of input states. When VCC = 0 V, leakage at 1Y and 2Y is limited to ±0.75 μA (max), preventing back-current into powered-down subsystems - verified across −40 °C to +125 °C per Table 8.

What is the maximum capacitive load 2Y can drive at 3.3 V while maintaining 5 ns propagation delay?

At VCC = 3.3 V, 2Y achieves tpd ≤5 ns with CL ≤15 pF (Table 9: 3.0–3.6 V range shows max 4.3 ns at CL = 5 pF, 4.9 ns at CL = 10 pF, 6.5 ns at CL = 15 pF). For strict ≤5 ns compliance, limit load to 10 pF including PCB trace and probe capacitance.

Is the Schmitt-trigger hysteresis voltage fixed or proportional to VCC?

Hysteresis is proportional to VCC: typical ΔV = 0.1 × VCC (Section 10, VIH/VIL specs show thresholds scaling linearly with supply). At 1.2 V, hysteresis ≈120 mV; at 3.3 V, ≈330 mV - ensuring consistent noise rejection across all supported rails without recalibration.