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Nexperia USA Inc. 74AUP2G06GN,132
- Part No.:
- 74AUP2G06GN,132
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Gates and Inverters
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP2G06GN,132.pdf
- Description:
- IC INVERTER 2CH 2-INP 6XSON
- Quantity:
- Payment:
- Shipping:
Inventory:5,000
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Product details
Overview
74AUP2G06GN,132 from Nexperia is a low-power dual inverter IC with open-drain outputs, Schmitt-trigger inputs, and IOFF partial power-down capability. It operates across 0.8 V to 3.6 V supply, delivers <0.9 μA max ICC, supports -40 °C to +125 °C, and enables wired-OR/AND logic in I²C bus and level-shifting interfaces.
For engineers reviewing the 74AUP2G06GN,132 datasheet, 74AUP2G06GN,132 pinout, 74AUP2G06GN,132 application, or 74AUP2G06GN,132 equivalent, this device serves as a robust, ultra-low-power logic buffer for voltage-level translation, bus arbitration, and noise-immune signal conditioning in space-constrained industrial and portable systems.
Technical Context
The 74AUP2G06GN implements two independent inverting buffers, each with Schmitt-trigger input thresholds (VIH ≥ 0.65×VCC, VIL ≤ 0.35×VCC) and open-drain NMOS output stages. Its IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V.
It uses advanced AUP (Advanced Ultra-low Power) CMOS technology to achieve sub-1 μA static current and propagation delays as low as 0.8 ns (VCC = 3.0–3.6 V, CL = 5 pF), while maintaining full JEDEC-compliant voltage tolerance up to 3.6 V on all inputs regardless of VCC.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 0.8 V to 3.6 V - supports single-supply operation across battery-powered, mixed-voltage, and I²C-compatible systems |
| Max ICC (Static) | 0.9 μA at 25 °C - enables multi-year battery life in always-on sensor nodes and wearables |
| Propagation Delay | 0.8 ns (min) at VCC = 3.3 V, CL = 5 pF - sufficient for 100+ MHz clocked logic in low-latency control paths |
| IOFF Leakage | ±0.75 μA at VCC = 0 V - prevents cross-talk and bus contention during hot-swap or partial system shutdown |
| Input Thresholds | VIL ≤ 0.35×VCC, VIH ≥ 0.65×VCC - ensures reliable switching with slow-rising signals and high noise immunity |
| ESD Rating | HBM >5000 V, CDM >1000 V - eliminates need for external ESD protection in handheld and industrial HMI designs |
| Operating Temp | -40 °C to +125 °C - qualified for under-hood automotive modules, industrial PLC I/O, and outdoor edge devices |
Pinout & Package
XSON6 package (SOT1115): extremely thin small outline, no leads, 6-terminal surface-mount package measuring 0.9 × 1.0 × 0.35 mm - optimized for high-density PCB layouts and automated assembly in compact consumer and IoT modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1A | Inverting buffer input channel 1 - accepts 0–3.6 V logic levels independent of VCC |
| 2 | GND | Ground reference - must be connected before VCC to ensure proper IOFF activation during power sequencing |
| 3 | 2A | Inverting buffer input channel 2 - electrically isolated from 1A; supports dual independent signal paths |
| 4 | 2Y | Open-drain output channel 2 - requires external pull-up to define HIGH state; enables wired-AND with other open-drain drivers |
| 5 | VCC | Supply voltage input - powers internal logic and enables IOFF control; decoupling capacitor required within 1 mm |
| 6 | 1Y | Open-drain output channel 1 - shares same electrical behavior as 2Y; allows parallel termination for bus arbitration |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Enables clean signal regeneration of slow or noisy edges (e.g., mechanical switch bounce, long PCB traces) without external hysteresis components |
| IOFF partial power-down | Prevents damaging back-current flow when VCC is off but I/O pins remain biased - critical for hot-pluggable modules and modular systems |
| Wide VCC range (0.8–3.6 V) | Eliminates level shifters between 1.2 V FPGA I/O, 1.8 V microcontrollers, and 3.3 V peripherals in heterogeneous SoC interconnects |
| Open-drain outputs | Supports active-LOW wired-OR and active-HIGH wired-AND logic - directly compatible with I²C, SMBus, and interrupt-sharing buses |
| Ultra-low dynamic power | CPD = 1.2 pF at 3.3 V - reduces switching power to <1 μW per transition at 1 MHz, ideal for duty-cycled sensing applications |
Applications
| Industrial Sensor Interface | I²C Bus Buffering |
|---|---|
|
Use Scenario: Connecting multiple analog sensor nodes with push-pull outputs to a shared microcontroller ADC input line. IC Role / Device Role / Timing Role: Dual inverter acts as noise-immune signal conditioner and level translator between 1.8 V sensors and 3.3 V MCU, with Schmitt inputs rejecting EMI-induced glitches. Use Value: Eliminates external RC filters and discrete transistors; reduces BOM count by 4 components per channel while improving signal integrity over 15 cm traces. |
Use Scenario: Extending I²C bus length beyond 1 m while supporting 10+ slave devices across two PCB segments. IC Role / Device Role / Timing Role: Open-drain inverters isolate bus segments and regenerate SDA/SCL signals, preserving timing margins and preventing capacitive loading collapse. Use Value: Enables reliable 400 kHz operation at 2.5 m total trace length; removes need for active repeaters or specialized I²C extenders. |
| Hot-Swappable Module Control | Low-Power Interrupt Aggregation |
|
Use Scenario: Managing power sequencing and status reporting for field-replaceable compute modules in telecom baseband units. IC Role / Device Role / Timing Role: Inverter channels translate module presence detect and fault signals between 1.2 V FPGA management logic and 3.3 V backplane monitoring circuitry. Use Value: IOFF function blocks leakage when module is removed, preventing false interrupts and backfeeding into powered-down subsystems. |
Use Scenario: Consolidating interrupt requests from three ultra-low-power motion sensors into a single wake-up line for an ARM Cortex-M0+ MCU in sleep mode. IC Role / Device Role / Timing Role: Wired-OR configuration of open-drain outputs allows any sensor to pull the shared interrupt line LOW without contention. Use Value: Reduces MCU wake-up latency by 3.2 μs vs. software polling; maintains <50 nA total system quiescent current during deep sleep. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual inverter with open-drain output applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G06DPWR | Higher ICC (max 10 μA), wider temp range (-40 °C to +125 °C), no IOFF, 5-V tolerant inputs | Lacks power-down isolation; unsuitable for hot-swap or partial-power systems | Select only if 5-V input compatibility is mandatory and system never operates with VCC = 0 V while I/O is active |
| 74LVC2G06GM,115 | Same XSON6 package, identical pinout, but lacks Schmitt-trigger inputs and IOFF; max ICC = 4 μA | Lower noise immunity; cannot drive slow-rising signals reliably; no back-current protection | Acceptable only in well-controlled, short-trace digital environments where input slew rates exceed 10 V/ns |
Compared with SN74LVC2G06DPWR and 74LVC2G06GM,115, the 74AUP2G06GN,132 uniquely combines sub-1 μA static power, Schmitt-trigger noise rejection, and IOFF-enabled safe power sequencing - making it the sole choice for battery-critical, mixed-voltage, or hot-plug-sensitive designs.
Availability
74AUP2G06GN,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, I²C bus extension, and low-power interrupt aggregation requiring stable component supply across extended temperature and ultra-low-power operating conditions.
Supply support for 74AUP2G06GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions with focus on efficiency, reliability, and miniaturization for industrial, automotive, and consumer markets.
The 74AUP2G06GN,132 belongs to Nexperia's Advanced Ultra-low Power (AUP) logic family, engineered specifically for energy-constrained, space-limited applications demanding robust noise immunity and seamless voltage-domain bridging.
FAQ
Can 74AUP2G06GN,132 be used without external pull-up resistors?
No. Its open-drain outputs require external pull-up resistors to define the HIGH logic state. Typical values range from 1 kΩ (for fast rise times in 3.3 V systems) to 10 kΩ (for ultra-low current in battery-powered applications). Pull-up voltage may differ from VCC - enabling true level shifting between domains.
Does the IOFF feature activate automatically when VCC drops below a threshold?
Yes. The IOFF circuit engages when VCC falls below approximately 0.2 V, disabling both outputs and limiting back-current to ±0.75 μA. This occurs independently of input states and requires no enable pin or external control - ensuring fail-safe behavior during brown-out or hot-removal events.
What is the maximum capacitive load the 74AUP2G06GN,132 can drive reliably?
It is characterized up to 30 pF load capacitance, with propagation delay increasing from 0.8 ns (CL = 5 pF) to 11.9 ns (CL = 30 pF) at VCC = 3.3 V. For loads exceeding 30 pF, signal integrity degrades due to increased rise/fall times; external buffering is recommended above 50 pF.
How does the Schmitt-trigger input improve performance in noisy environments?
Schmitt-trigger inputs provide hysteresis (typically 0.3×VCC), meaning the rising threshold (VIH) is significantly higher than the falling threshold (VIL). This prevents multiple toggles on slowly changing or noisy signals - such as those from thermistors, rotary encoders, or unshielded cables - ensuring one clean transition per input edge.
74AUP2G06GN,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Inverter
- Number of Circuits:
- 2
- Number of Inputs:
- 2
- Features:
- Open Drain
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Max):
- 500 nA
- Current - Output High, Low:
- -, 4mA
- Input Logic Level - Low:
- 0.7V ~ 0.9V
- Input Logic Level - High:
- 1.6V ~ 2V
- Max Propagation Delay @ V, Max CL:
- 10.5ns @ 3.3V, 30pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON (0.9x1)
74AUP2G06GN,132 FAQ
1.How can I place an order for 74AUP2G06GN,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G06GN,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G06GN,132 reliable?
The price and inventory of 74AUP2G06GN,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G06GN,132 is usually 5 days.
3.What payment methods are accepted for 74AUP2G06GN,132?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP2G06GN,132 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP2G06GN,132?
74AUP2G06GN,132 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP2G06GN,132 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G06GN,132?
For technical support, including 74AUP2G06GN,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G06GN,132 requirements.
6.How does Aetrix verify that 74AUP2G06GN,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G06GN,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G06GN,132 meets industry standards.
7.What is the process for return or replacement of 74AUP2G06GN,132?
All 74AUP2G06GN,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G06GN,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G06GN,132 part is unused and in its original packaging.
Return procedure for 74AUP2G06GN,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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