Nexperia USA Inc. 74AUP2G06GW,125

Overview

74AUP2G06GW,125 from Nexperia is a low-power dual inverter IC with open-drain outputs, designed for level-shifting and wired-OR logic implementation in ultra-low-voltage systems. It operates across 0.8 V to 3.6 V supply, features Schmitt-trigger inputs for noise immunity, delivers ≤0.9 μA max ICC, supports partial power-down via IOFF, and is rated for −40 °C to +125 °C operation.

For engineers reviewing the 74AUP2G06GW,125 datasheet, 74AUP2G06GW,125 pinout, 74AUP2G06GW,125 application, or 74AUP2G06GW,125 equivalent, this device is selected for battery-powered I²C bus pull-up, GPIO signal inversion with voltage translation, and multi-source active-LOW arbitration in space-constrained embedded control nodes.

Technical Context

The 74AUP2G06GW,125 implements two independent inverting buffers, each with an open-drain output enabling wired-OR/AND logic when connected to shared bus lines. Its Schmitt-trigger inputs provide hysteresis (typ. 0.15 × VCC) across the full 0.8–3.6 V range, ensuring robust switching despite slow-rising signals.

IOFF circuitry actively disables outputs during power-down, limiting backflow current to ±0.75 μA at VCC = 0 V, while static power consumption remains ≤1.4 μA over −40 °C to +125 °C. Propagation delay ranges from 0.8 ns (VCC = 3.3 V, CL = 5 pF) to 21.3 ns (VCC = 1.2 V, CL = 30 pF), supporting sub-MHz to ~100 MHz toggle rates depending on load and supply.

Key Specifications

Pinout & Package

TSSOP6 (SOT363-2) package: plastic thin shrink small outline, 6-pin, 1.25 mm body width, 0.65 mm lead pitch, exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual inverter with open-drain output applications.

Compared with 74LVC2G06GW,125 and SN74AUP2G06DBVR, the 74AUP2G06GW,125 uniquely combines ultra-low ICC (<1.4 μA), true 0.8 V operation, and IOFF-enabled power-domain isolation-making it the sole option for energy-critical, multi-voltage, or hot-pluggable embedded subsystems.

Availability

74AUP2G06GW,125 is available at Aetrix Electronics and suitable for battery-powered IoT endpoints, industrial sensor nodes, and portable medical monitors requiring stable component supply, extended temperature support, and guaranteed long-term manufacturability.

Supply support for 74AUP2G06GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable, and scalable logic, power, and analog solutions for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) logic family targets ultra-low-power portable and battery-operated applications, emphasizing sub-1 μA static current, wide VCC flexibility, and robust IOFF functionality for modern mixed-voltage system architectures.

FAQ

Can 74AUP2G06GW,125 drive a 10 kΩ pull-up to 3.3 V while maintaining VOL ≤ 0.4 V?

Yes. At VCC = 3.3 V and IO = 0.33 mA (3.3 V / 10 kΩ), the datasheet specifies VOL ≤ 0.45 V (max) at 4 mA sink, and typical VOL is <0.1 V at 0.33 mA. This provides >2.85 V HIGH margin and <0.4 V LOW margin, fully compliant with 3.3 V CMOS input thresholds.

Does the IOFF feature work when VCC = 0.2 V?

Yes. The datasheet confirms ΔIOFF ≤ ±0.75 μA when VCC is between 0 V and 0.2 V, and IOFF remains active across the full 0–0.2 V range. Output is placed in high-impedance state, preventing back-current even during brown-out or controlled ramp-down sequences.

What is the maximum capacitive load the outputs can drive while staying within tpd < 5 ns at 3.3 V?

At VCC = 3.3 V, tpd ≤ 4.0 ns (max) for CL = 10 pF and ≤ 5.4 ns (max) for CL = 15 pF. Therefore, the maximum verified load for <5 ns delay is 15 pF - including PCB trace capacitance (~0.15 pF/mm), probe/jig effects, and any downstream gate input capacitance.

Is the Schmitt-trigger hysteresis voltage specified over temperature?

Yes. Hysteresis is derived from VIH and VIL specifications: at VCC = 3.3 V, VIH(min) = 2.0 V and VIL(max) = 0.9 V, yielding ≥1.1 V hysteresis. Over −40 °C to +125 °C, minimum hysteresis remains ≥0.15 × VCC, ensuring consistent noise rejection across full operating range.