Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Buffers, Drivers, Receivers, Transceivers

Nexperia USA Inc. 74AUP2G07GN,132

Name: 74AUP2G07GN,132
Brand: Nexperia USA Inc.
SKU: 74AUP2G07GN,132
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 74AUP2G07GN,132

Manufacturer:: Nexperia USA Inc.

Category:: Buffers, Drivers, Receivers, Transceivers

Package:: 6-XFDFN

Datasheet:: 74AUP2G07GN,132.pdf

Description:: IC BUFFER NON-INVERT 3.6V 6XSON

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:277,240

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

74AUP2G07GN,132 from NXP Semiconductors is a dual non-inverting buffer with open-drain outputs, designed for level translation and wired-OR logic in ultra-low-power applications. It operates from 0.8 V to 3.6 V, delivers ±20 mA output drive at V_CC = 3.3 V, and features 2.4 ns typical propagation delay at 3.3 V.

For engineers reviewing the 74AUP2G07GN,132 datasheet, 74AUP2G07GN,132 pinout, 74AUP2G07GN,132 application, or 74AUP2G07GN,132 equivalent, key selection criteria include supply voltage range, open-drain compatibility with I²C and SMBus, propagation delay vs. power trade-off, and GN package thermal performance in space-constrained PCB layouts.

Technical Context

This device belongs to the 74AUP (Advanced Ultra-low Power) logic family, optimized for sub-1-V operation while maintaining noise immunity and rail-to-rail input thresholds. Its dual independent buffers support asynchronous signal conditioning without internal feedback paths or latch-up risk.

Each channel implements a CMOS input stage with hysteresis-free threshold tracking across V_CC, and an NMOS-only open-drain output stage requiring external pull-up for logic high assertion. No internal ESD protection diodes connect outputs to V_CC, enabling true bidirectional level shifting.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage Range	0.8 V to 3.6 V - supports direct interface between 1.2 V, 1.8 V, 2.5 V, and 3.3 V domains without level shifters
Output Type	Open-drain - enables wired-OR bus topologies and I²C/SMBus compliance with external pull-up
Max Propagation Delay	3.4 ns at V_CC = 3.3 V, C_L = 15 pF - ensures timing integrity in high-speed digital control loops
I_OH/I_OL	±20 mA at V_CC = 3.3 V - sufficient to drive multiple standard CMOS loads or LED indicators
Quiescent Current	0.9 µA typical at V_CC = 3.3 V - minimizes standby power in battery-operated sensor nodes
Input Threshold	V_IH = 0.65×V_CC, V_IL = 0.35×V_CC - guarantees robust noise margin across full supply range

Pinout & Package

Supplied in a 6-pin XSON-6 (GN) package, 1.45 mm × 1.2 mm, 0.5 mm pitch, with exposed die pad for thermal enhancement and mechanical stability.

Pin/Terminal	Circuit Role	Design Meaning
1	Input A1	CMOS-compatible digital input for first buffer channel
2	Output Y1	Open-drain output - requires external pull-up resistor to define high-level voltage
3	GND	Ground reference for both logic and output stages
4	V_CC	Positive supply - sets logic thresholds and output drive capability
5	Input A2	CMOS-compatible digital input for second independent buffer channel
6	Output Y2	Open-drain output - electrically isolated from Y1, supports separate pull-up networks

Key Features

Feature	Design Value
Ultra-low static power	Sub-1 µA I_CC enables multi-year operation on coin-cell batteries in IoT endpoints
Wide V_CC range	Single part replaces three voltage-specific buffers (1.2 V/1.8 V/3.3 V), reducing BOM count
Open-drain outputs	Eliminates bus contention in shared-line systems like I²C clock stretching and interrupt aggregation
GN package footprint	1.45 mm × 1.2 mm area saves >60% board space versus SO-6, critical for wearables and medical patches

Applications

Industrial Sensor Interface

I²C Bus Buffering

Use Scenario: Connecting multiple analog sensor ADCs with different supply rails to a single microcontroller I/O port.

IC Role / Device Role / Timing Role: Level-translating buffer isolating 1.8 V sensor logic from 3.3 V host MCU while preserving signal edge rate.

Use Value: Eliminates need for discrete MOSFET translators; maintains <3.5 ns propagation delay across voltage domains.

Use Scenario: Extending I²C bus length beyond 1 m by buffering SDA/SCL lines between master and slave segments.

IC Role / Device Role / Timing Role: Open-drain repeater enabling bidirectional signal pass-through with controlled rise/fall times.

Use Value: Supports 400 kHz Fast-mode I²C without clock stretching; reduces bus capacitance loading by 50% per segment.

Wearable Health Monitor

Low-Power GPIO Expander Interface

Use Scenario: Driving LED status indicators from a 1.2 V PMIC-controlled MCU GPIO in a hearable device.

IC Role / Device Role / Timing Role: Voltage-tolerant buffer allowing 3.3 V LED anode pull-up while accepting 1.2 V logic input.

Use Value: Enables bright LED visibility without boosting MCU I/O voltage; draws only 0.9 µA quiescent current.

Use Scenario: Interfacing a low-voltage I/O expander (e.g., PCA9536) to a higher-voltage system controller.

IC Role / Device Role / Timing Role: Bidirectional level shifter for expander interrupt and configuration lines.

Use Value: Prevents back-powering of expander during sleep; supports hot-plug detection via open-drain edge sensing.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual open-drain buffer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC2G07DBVR	Wider V_CC range (1.65–5.5 V); higher I_OL (32 mA); 5.5 ns t_PD at 3.3 V	Not suitable below 1.65 V; incompatible with 1.2 V logic domains	Select when interfacing 5 V peripherals or requiring higher sink current
74LVC2G17GW,125	Schmitt-trigger inputs; same V_CC range (1.65–5.5 V); no sub-1-V operation	Introduces hysteresis (±100 mV), unsuitable for clean digital waveform re-driving	Choose only where noisy signal conditioning is required, not for pure level translation

Compared with SN74LVC2G07DBVR and 74LVC2G17GW,125, the 74AUP2G07GN,132 uniquely supports 0.8 V operation and delivers lowest static current, making it the sole option for energy-harvesting and coin-cell-powered designs requiring dual open-drain buffering.

Availability

74AUP2G07GN,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable health monitors, I²C bus extension, and low-power GPIO expansion requiring stable component supply across long-lifecycle programs.

Supply support for 74AUP2G07GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The 74AUP logic family targets ultra-low-power portable and energy-constrained applications, delivering sub-1-V operation and nanowatt static power without sacrificing speed or noise immunity.

FAQ

Can 74AUP2G07GN,132 be used with 5 V pull-up resistors?

Yes - its open-drain outputs tolerate up to 5.5 V on Y1/Y2 pins regardless of V_CC, enabling safe interface with 5 V buses. The input thresholds remain referenced to V_CC, so 5 V signals applied directly to A1/A2 will exceed absolute maximum ratings and must be clamped or attenuated.

Does this device support hot insertion?

Yes - the absence of input-to-V_CC ESD diodes and rail-to-rail input structure allows A1/A2 pins to be driven before V_CC is applied, preventing back-powering and enabling true hot-swap capability in modular sensor systems.

What is the minimum recommended pull-up resistor value?

For 3.3 V pull-up and 400 kHz I²C operation, 2.2 kΩ is recommended to meet rise-time requirements (≤300 ns) while limiting sink current to ≤1.5 mA per output under worst-case conditions.

Is the GN package RoHS-compliant and lead-free?

Yes - the XSON-6 (GN) package uses lead-free solderable terminations and complies with EU RoHS Directive 2011/65/EU and JEDEC J-STD-020 moisture sensitivity level 1 (MSL-1), suitable for standard reflow assembly without special handling.

74AUP2G07GN,132 Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: 74AUP

Package/Case:: 6-XFDFN

Packaging:: Bulk

Product Status:: Active

Logic Type:: Buffer, Non-Inverting

Number of Elements:: 2

Number of Bits per Element:: 1

Input Type:: -

Output Type:: Open Drain

Current - Output High, Low:: -, 4mA

Voltage - Supply:: 0.8V ~ 3.6V

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 6-XSON (0.9x1)

74AUP2G07GN,132 FAQ

1.How can I place an order for 74AUP2G07GN,132 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP2G07GN,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AUP2G07GN,132 reliable?

The price and inventory of 74AUP2G07GN,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G07GN,132 is usually 5 days.

3.What payment methods are accepted for 74AUP2G07GN,132?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP2G07GN,132 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74AUP2G07GN,132?

74AUP2G07GN,132 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74AUP2G07GN,132 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74AUP2G07GN,132?

For technical support, including 74AUP2G07GN,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G07GN,132 requirements.

6.How does Aetrix verify that 74AUP2G07GN,132 is sourced from the original manufacturer or authorized distributors?

All 74AUP2G07GN,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G07GN,132 meets industry standards.

7.What is the process for return or replacement of 74AUP2G07GN,132?

All 74AUP2G07GN,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G07GN,132, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP2G07GN,132 part is unused and in its original packaging.

Return procedure for 74AUP2G07GN,132:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…