Nexperia USA Inc. 74AUP2G07GS,132

Overview

74AUP2G07GS,132 from Nexperia is a dual CMOS buffer with open-drain outputs and Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply. It delivers ultra-low static current (≤1.4 μA at −40 °C to +125 °C), supports partial power-down via IOFF circuitry, and features overvoltage-tolerant inputs up to 3.6 V. Used in level-shifting I²C bus interfaces and low-power sensor signal conditioning.

For engineers reviewing the 74AUP2G07GS,132 datasheet, 74AUP2G07GS,132 pinout, 74AUP2G07GS,132 application, or 74AUP2G07GS,132 equivalent, this device serves as a low-noise, rail-flexible buffer for mixed-voltage digital interfacing where leakage control, ESD robustness (HBM >5 kV), and sub-10 ns propagation delay at 3.3 V are critical selection criteria.

Technical Context

This device implements two independent non-inverting buffers, each with Schmitt-trigger input thresholds (VIH ≥0.65×VCC, VIL ≤0.35×VCC) enabling noise-immune operation on slow-rising signals. The open-drain outputs support wired-AND logic and bidirectional bus driving without contention.

IOFF circuitry actively disables output terminals when VCC = 0 V, limiting backflow current to ±0.75 μA and enabling hot-insertion in partial-power-down systems. Input and output pins tolerate up to 4.6 V regardless of VCC, simplifying interface to higher-voltage domains.

Key Specifications

Pinout & Package

XSON6 package (SOT1202): plastic extremely thin small outline, no leads, 6-terminal surface-mount, body size 1.0 mm × 1.0 mm × 0.35 mm, thermal pad optional, pin 1 marked by indentation below marking code 'p7'.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual open-drain buffer applications.

Compared with SN74LVC2G07DBVR and 74LVC2G17GW,125, the 74AUP2G07GS,132 uniquely combines sub-1 μA static current, Schmitt-trigger noise immunity, open-drain flexibility, and 0.8 V operation-making it the sole choice for battery-constrained, mixed-voltage, noise-prone embedded interfaces.

Availability

74AUP2G07GS,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, I²C level shifting, low-power wearable systems, and hot-swappable module interfaces requiring stable component supply across extended temperature ranges.

Supply support for 74AUP2G07GS,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in consumer, industrial, and automotive applications.

The 74AUP (Advanced Ultra Low Power) product line targets ultra-low-power digital interfacing in space- and energy-constrained systems, emphasizing rail flexibility, leakage control, and robustness in harsh thermal and electrical environments.

FAQ

Can 74AUP2G07GS,132 drive a 10 kΩ pull-up resistor at 3.3 V while maintaining VOL ≤0.4 V?

Yes. At VCC = 3.3 V and IO = 4.0 mA, VOL is guaranteed ≤0.50 V over −40 °C to +125 °C. With a 10 kΩ pull-up to 3.3 V, output current is ~0.33 mA - well within the 4 mA test condition, ensuring VOL remains <0.2 V per typical data and meeting I²C standard requirements.

Does the IOFF feature activate automatically when VCC drops below a threshold?

Yes. IOFF circuitry engages when VCC = 0 V, disabling both outputs and limiting OFF-state leakage to ±0.75 μA. It does not require external control - activation is intrinsic to the power rail state and functions across the full −40 °C to +125 °C range without biasing or enable signals.

Is the 74AUP2G07GS,132 pin-compatible with other 74AUP2Gxx devices in XSON6 packages?

No. While all 74AUP2Gxx XSON6 variants share the SOT1202 footprint, pin assignments differ: 74AUP2G07 uses pins 1/3/4/5/6 for 1A/GND/2A/2Y/VCC/1Y, whereas 74AUP2G17 places 1A/1Y/GND/2A/2Y/VCC on same pins - swapping VCC and 1Y positions. PCB layout is not interchangeable.

What is the maximum capacitive load the 74AUP2G07GS,132 can drive while maintaining tPD ≤5 ns at 3.3 V?

At VCC = 3.3 V and CL = 15 pF, tPD is guaranteed ≤5.0 ns over −40 °C to +125 °C. Driving >15 pF increases delay nonlinearly - e.g., at CL = 30 pF, tPD reaches 11.4 ns max. For timing-critical paths requiring <5 ns, keep total load ≤15 pF including trace and probe capacitance.