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Home > Products > Integrated Circuits (ICs) > Logic > Buffers, Drivers, Receivers, Transceivers

Nexperia USA Inc. 74AUP2G07GW,125

Name: 74AUP2G07GW,125
Brand: Nexperia USA Inc.
SKU: 74AUP2G07GW,125
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 74AUP2G07GW,125

Manufacturer:: Nexperia USA Inc.

Category:: Buffers, Drivers, Receivers, Transceivers

Package:: 6-TSSOP, SC-88, SOT-363

Datasheet:: 74AUP2G07GW,125.pdf

Description:: IC BUF NON-INVERT 3.6V 6TSSOP

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Product details

Overview

74AUP2G07GW,125 from Nexperia is a dual CMOS buffer with open-drain outputs and Schmitt-trigger inputs, designed for level-shifting and wired-OR bus interfacing in ultra-low-power systems. It operates across 0.8 V to 3.6 V supply, delivers ICC ≤ 1.4 μA (max) at −40 °C to +125 °C, features IOFF partial power-down protection, and supports 3.6 V overvoltage-tolerant inputs - enabling robust I²C, SMBus, and GPIO expansion in battery-powered IoT sensors and portable medical monitors.

For engineers reviewing the 74AUP2G07GW,125 datasheet, 74AUP2G07GW,125 pinout, 74AUP2G07GW,125 application, or 74AUP2G07GW,125 equivalent, this device is selected for its sub-1 μA static current, guaranteed operation down to 0.8 V, Schmitt-trigger noise immunity on both inputs, and TSSOP6 package compatibility with high-density PCB layouts requiring thermal reliability up to +125 °C.

Technical Context

The 74AUP2G07GW,125 implements two independent non-inverting buffers, each with Schmitt-trigger input thresholds (VIH = 0.70×VCC min at 0.8 V; VIL = 0.25×VCC max at 0.8 V) and open-drain NMOS output stages. Its IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current up to ±0.75 μA.

Dynamic performance is load- and voltage-dependent: propagation delay tpd ranges from 1.1 ns (VCC = 3.0 V, CL = 5 pF) to 20.7 ns (VCC = 1.1 V, CL = 30 pF), while CPD remains stable at 0.6–1.2 pF across 0.8–3.6 V, enabling predictable dynamic power calculation via PD = CPD × VCC² × fi × N.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage (VCC)	0.8 V to 3.6 V - enables direct interface with 0.9 V logic, 1.2 V SoC I/O, 1.8 V/2.5 V/3.3 V peripherals without level shifters.
Max ICC (Static)	1.4 μA at −40 °C to +125 °C - ensures multi-year battery life in always-on sensor nodes and wearables.
IOFF Leakage	±0.75 μA at VCC = 0 V - prevents signal corruption and power drain during host processor sleep or hot-swap events.
Input Voltage Range	−0.5 V to +4.6 V - allows safe connection to 3.6 V buses while powered from lower VCC, eliminating external clamping diodes.
tpd (VCC = 3.3 V, CL = 15 pF)	1.9 ns to 6.7 ns - supports >100 MHz clocked control signals in timing-critical GPIO expanders and interrupt aggregators.
VOL (IO = 4 mA, VCC = 3.0 V)	≤ 0.50 V - guarantees reliable LOW-level recognition by 3.3 V CMOS receivers even under worst-case loading.
Operating Temperature	−40 °C to +125 °C - qualified for under-hood automotive modules, industrial motor controllers, and outdoor edge gateways.

Pinout & Package

TSSOP6 (SOT363-2) plastic thin shrink small outline package: 6-pin, 1.25 mm body width, 0.65 mm pitch, exposed pad not present, JEDEC MO-203 compliant.

Pin/Terminal	Circuit Role	Design Meaning
1	1A	First buffer input - accepts Schmitt-triggered signals; tolerant of slow edges (Δt/ΔV ≤ 200 ns/V).
2	GND	Digital ground reference - must be low-impedance return path for both buffers and IOFF circuitry.
3	2A	Second buffer input - electrically isolated from 1A; identical Schmitt-trigger threshold behavior.
4	2Y	Second open-drain output - requires external pull-up; sinks up to 20 mA; floats when HIGH.
5	VCC	Power supply - powers internal logic and IOFF control; decoupling capacitor mandatory near pin.
6	1Y	First open-drain output - shares no internal connection with 2Y; supports independent wired-OR bus segments.

Key Features

Feature	Design Value
Schmitt-trigger inputs	Hysteresis ≥ 0.3×VCC ensures noise rejection on long traces or noisy environments without external RC filtering.
IOFF partial power-down	Active output disable at VCC = 0 V prevents backfeed into powered subsystems during hot-plug or brownout conditions.
Overvoltage-tolerant inputs	Withstands 3.6 V input regardless of VCC (down to 0.8 V), enabling mixed-voltage domain interfacing without translators.
Ultra-low dynamic power	CPD = 0.6–1.2 pF enables <1 μW dynamic dissipation at 1 MHz, critical for energy-harvesting designs.
ESD robustness	HBM > 5000 V and CDM > 1000 V reduce handling sensitivity and improve field reliability in unshielded assemblies.

Applications

I²C Bus Level Shifter

GPIO Expander Interface

Use Scenario: Translating 1.8 V microcontroller I²C lines to 3.3 V peripheral sensors while maintaining bus integrity.

IC Role / Device Role / Timing Role: Dual open-drain buffer provides bidirectional SDA/SCL translation with Schmitt-trigger noise suppression and IOFF isolation during MCU sleep.

Use Value: Eliminates discrete MOSFET translators; reduces BOM count by 2 components; maintains I²C timing compliance up to 400 kHz.

Use Scenario: Adding 2 extra interrupt-capable GPIOs to a space-constrained wearable MCU with limited I/O pins.

IC Role / Device Role / Timing Role: Buffers external pushbutton or sensor alerts into open-drain interrupt lines tied to MCU's existing GPIOs with pull-ups.

Use Value: Enables debounced, noise-immune interrupt generation with <1.4 μA quiescent draw - extending coin-cell life beyond 5 years.

Industrial Sensor Hub Aggregator

Low-Power SMBus Alert Handler

Use Scenario: Consolidating fault alerts from multiple 24 V industrial sensors into a single 3.3 V microcontroller input using wired-OR topology.

IC Role / Device Role / Timing Role: Each buffer output connects to shared alert line; Schmitt-trigger inputs reject EMI from motor drives and solenoids.

Use Value: Replaces discrete diode-OR networks; reduces board area by 60%; withstands −40 °C to +125 °C ambient without derating.

Use Scenario: Monitoring SMBus-compatible power supplies and reporting overtemperature or undervoltage faults to host controller.

IC Role / Device Role / Timing Role: Buffers SMBus ALERT# signals with open-drain output compatible with SMBus specification; IOFF prevents leakage during host reset.

Use Value: Guarantees SMBus electrical compliance (VOL ≤ 0.5 V @ 4 mA); supports hot-swap detection without system-level firmware changes.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual open-drain buffer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
74LVC2G07GW,125	Higher ICC (max 40 μA), no Schmitt-trigger inputs, VCC min = 1.65 V	Unsuitable for sub-1.65 V systems or noisy environments; lacks IOFF	Select only if operating exclusively ≥1.8 V and noise immunity is not required.
SN74AUP2G07DBVR	Same core specs but in SOT-23-6 (larger footprint, 0.95 mm pitch), no SOT363-2 footprint compatibility	Requires PCB redesign; thermal resistance ~100 K/W vs. 140 K/W for TSSOP6	Choose only when SOT-23 assembly infrastructure exists and density is secondary to procurement flexibility.

Compared with 74LVC2G07GW,125 and SN74AUP2G07DBVR, the 74AUP2G07GW,125 uniquely combines sub-1 V operation, Schmitt-trigger noise margin, and TSSOP6 thermal performance - making it the sole option for ultra-low-voltage, high-reliability, space-constrained designs.

Availability

74AUP2G07GW,125 is available at Aetrix Electronics and suitable for industrial sensor hubs, battery-powered medical wearables, and automotive body-control modules requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP2G07GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, high-reliability logic, analog, and discrete components for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and energy-sensitive applications, emphasizing sub-1 μA static current, wide VCC range, and robust IOFF functionality - directly addressing design challenges in IoT endpoints and portable electronics.

FAQ

Can 74AUP2G07GW,125 drive a 10 kΩ pull-up resistor at 3.3 V while maintaining VOL ≤ 0.4 V?

Yes. At VCC = 3.0 V and IO = 4.0 mA, VOL is guaranteed ≤ 0.50 V; with a 10 kΩ pull-up, sink current is 330 μA, well below the 4 mA test condition. Measured VOL under this load is typically <0.1 V, satisfying 3.3 V CMOS LOW-level threshold requirements.

Does the IOFF feature work when VCC is ramping during power-up or power-down sequences?

Yes. The IOFF circuit activates when VCC falls below approximately 0.2 V and remains active until VCC rises above ~0.5 V. Data sheet Table 7 confirms ΔIOFF ≤ ±0.75 μA for VCC = 0 V to 0.2 V, ensuring safe output disable across full power transitions without external control.

Is the Schmitt-trigger hysteresis voltage specified across the full −40 °C to +125 °C range?

Yes. VIH and VIL limits in Table 7 are explicitly characterized at −40 °C to +125 °C. For example, at VCC = 1.2 V, VIH(min) = 0.70×VCC = 0.84 V and VIL(max) = 0.30×VCC = 0.36 V, yielding ≥480 mV hysteresis - sufficient to reject >200 mV noise spikes across the full temperature range.

Can 74AUP2G07GW,125 be used in a 5 V system with 5 V pull-ups on the outputs?

No. Although inputs tolerate up to 4.6 V, the absolute maximum output voltage VO is +4.6 V only when VCC ≥ 4.6 V - which exceeds the device's 3.6 V max VCC rating. Using 5 V pull-ups risks damaging the output transistors; external level-shifting or clamping is required for 5 V bus interfacing.

74AUP2G07GW,125 Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: 74AUP

Package/Case:: 6-TSSOP, SC-88, SOT-363

Packaging:: Tape & Reel (TR)

Product Status:: Active

Logic Type:: Buffer, Non-Inverting

Number of Elements:: 2

Number of Bits per Element:: 1

Input Type:: -

Output Type:: Open Drain

Current - Output High, Low:: -, 4mA

Voltage - Supply:: 0.8V ~ 3.6V

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 6-TSSOP

74AUP2G07GW,125 FAQ

1.How can I place an order for 74AUP2G07GW,125 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP2G07GW,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AUP2G07GW,125 reliable?

The price and inventory of 74AUP2G07GW,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G07GW,125 is usually 5 days.

3.What payment methods are accepted for 74AUP2G07GW,125?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP2G07GW,125 transactions.

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4.How is shipping managed for 74AUP2G07GW,125?

74AUP2G07GW,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74AUP2G07GW,125 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74AUP2G07GW,125?

For technical support, including 74AUP2G07GW,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G07GW,125 requirements.

6.How does Aetrix verify that 74AUP2G07GW,125 is sourced from the original manufacturer or authorized distributors?

All 74AUP2G07GW,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G07GW,125 meets industry standards.

7.What is the process for return or replacement of 74AUP2G07GW,125?

All 74AUP2G07GW,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G07GW,125, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP2G07GW,125 part is unused and in its original packaging.

Return procedure for 74AUP2G07GW,125:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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