Nexperia USA Inc. 74AUP2G07GXZ

Overview

74AUP2G07GX from Nexperia is a dual CMOS buffer with open-drain outputs and Schmitt-trigger inputs, designed for level-shifting and wired-OR bus interfacing in ultra-low-power systems. It operates across 0.8 V to 3.6 V supply, delivers ≤0.9 μA max ICC at 25 °C, supports partial power-down via IOFF, and is rated for -40 °C to +125 °C ambient. Used in I²C pull-up control, GPIO expansion, and low-voltage sensor interface circuits.

For engineers reviewing the 74AUP2G07GX datasheet, 74AUP2G07GX pinout, 74AUP2G07GX application, or 74AUP2G07GX equivalent, this page provides verified functional identity, validated X2SON6 (SOT1255-2) package mapping, confirmed 6-terminal pin assignment, real-world timing behavior at 1.2 V/1.8 V/3.3 V, and cross-reference alternatives with documented voltage and drive capability differences.

Technical Context

This device implements two independent non-inverting buffers, each with Schmitt-trigger input thresholds (VIH ≥0.65×VCC, VIL ≤0.35×VCC) enabling robust noise immunity against slow-rising signals. The open-drain outputs support bidirectional bus operation and require external pull-ups, with VOL ≤0.50 V at IO = 4.0 mA and VCC = 3.0 V.

IOFF circuitry actively disables output terminals when VCC = 0 V, limiting backflow current to ±0.75 μA and enabling safe hot-insertion in multi-rail systems. Propagation delay ranges from 1.1 ns (VCC = 3.3 V, CL = 5 pF) to 11.4 ns (VCC = 0.8 V, CL = 30 pF), scaling predictably with load capacitance and supply voltage.

Key Specifications

Pinout & Package

X2SON6 plastic thermal-enhanced extremely thin small outline package (SOT1255-2); 6-terminal, no leads; body dimensions 1.0 mm × 0.8 mm × 0.32 mm; exposed thermal pad not electrically connected; pin 1 index located at lower-left corner below marking code 'p7'.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual open-drain buffer applications.

Compared with 74LVC2G07GW and SN74AUP2G07DBVR, the 74AUP2G07GX uniquely combines sub-1 V operation, IOFF protection, and the smallest X2SON6 footprint-making it optimal for ultra-dense, multi-rail, battery-operated designs where leakage control and board area are critical.

Availability

74AUP2G07GX is available at Aetrix Electronics and suitable for I²C bus translation, GPIO expansion, low-power sensor hub design, and industrial digital input modules requiring stable component supply across automotive-grade temperature ranges.

Supply support for 74AUP2G07GX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-volume, high-reliability logic, analog, and MOSFET solutions, with manufacturing rooted in process optimization and automotive-grade quality systems.

The 74AUP (Advanced Ultra-low Power) logic family targets energy-constrained applications including portable medical devices, smart meters, and wireless sensor networks-prioritizing nanowatt static power and wide-voltage interoperability.

FAQ

Can 74AUP2G07GX drive a 10 kΩ pull-up to 3.3 V while powered from 1.8 V?

Yes. With VCC = 1.8 V and IO = 0.33 mA (3.3 V / 10 kΩ), VOL remains ≤0.35 V per datasheet Table 7 (Tamb = −40 °C to +125 °C), ensuring valid LOW-level recognition by 3.3 V receivers. The open-drain architecture decouples output voltage from VCC, enabling true level-shifting.

Does the IOFF feature activate automatically during power sequencing?

Yes. IOFF engages when VCC falls below approximately 0.2 V, disabling both outputs and limiting back-current to ±0.75 μA regardless of input/output voltage states. No enable/disable pin or external control is required-behavior is intrinsic to the silicon design.

What is the maximum capacitive load the outputs can drive while maintaining tpd < 5 ns at 3.3 V?

At VCC = 3.3 V, propagation delay stays below 5 ns for CL ≤ 15 pF (typical tpd = 4.0 ns, max = 5.7 ns). For CL = 30 pF, tpd rises to 11.4 ns max. Layout parasitics must be included in total CL; keep trace lengths short and avoid stubs to stay within timing budget.

Is the X2SON6 (SOT1255-2) package compatible with standard reflow profiles for lead-free assembly?

Yes. SOT1255-2 is qualified for IPC/JEDEC J-STD-020 moisture sensitivity level 1 (MSL1) and supports peak reflow temperatures up to 260 °C. Its 0.32 mm height and thermal-enhanced construction ensure reliable solder joint formation under standard Pb-free profiles without tombstoning.