Nexperia USA Inc. 74AUP2G08GT,115

Overview

74AUP2G08GT,115 from Nexperia is a low-power dual 2-input AND gate in an XSON8 package (SOT833-1), operating across 0.8 V to 3.6 V supply voltage with Schmitt-trigger inputs for noise immunity and IOFF circuitry enabling partial power-down mode. It delivers propagation delay as low as 0.9 ns at 3.0 V (CL = 5 pF) and static ICC ≤ 0.9 μA max, supporting battery-powered sensor interfaces and portable logic level translation.

For engineers reviewing the 74AUP2G08GT,115 datasheet, 74AUP2G08GT,115 pinout, 74AUP2G08GT,115 application, or 74AUP2G08GT,115 equivalent, key selection criteria include ultra-low static/dynamic power consumption, overvoltage-tolerant inputs up to 3.6 V, guaranteed operation from –40 °C to +125 °C, and compatibility with 1.2 V, 1.8 V, and 3.3 V logic systems.

Technical Context

This device implements two independent AND gates with Schmitt-trigger inputs-each accepting slow-rising/falling signals without oscillation-and features IOFF circuitry that disables outputs during power-down to prevent backflow current. Its rail-to-rail input tolerance (–0.5 V to +4.6 V) and output drive capability (±20 mA) support mixed-voltage interconnects.

The logic function conforms strictly to standard AND truth table behavior (L/L→L, L/H→L, H/L→L, H/H→H), with propagation delays characterized across VCC (0.8–3.6 V), temperature (–40 °C to +125 °C), and load capacitance (5–30 pF). Input hysteresis ensures robust switching in noisy environments.

Key Specifications

Pinout & Package

XSON8 plastic extremely thin small outline package (SOT833-1); no leads; 8 terminals; body dimensions 1.0 mm × 1.95 mm × 0.5 mm; thermal pad absent; pin 1 indicator located below marking code in lower-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual 2-input AND gate applications.

Compared with SN74LVC2G08DBVR and 74LVC2G08GW,125, the 74AUP2G08GT,115 uniquely combines ultra-low ICC (<1 μA), full –40 °C to +125 °C qualification, Schmitt inputs, and IOFF-making it the sole choice for energy-constrained, thermally harsh, or mixed-voltage safety-critical logic gating.

Availability

74AUP2G08GT,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable device power control, automotive body control modules, and IoT edge node signal conditioning requiring stable component supply across extended temperature ranges and ultra-low power budgets.

Supply support for 74AUP2G08GT,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in automotive, industrial, and mobile markets.

The 74AUP (Advanced Ultra-low Power) logic family targets battery-operated and thermally constrained applications where nanowatt static power, wide VCC scalability, and robust noise immunity are mandatory design requirements.

FAQ

Does 74AUP2G08GT,115 support true bidirectional signal flow?

No. The 74AUP2G08GT,115 is a unidirectional AND gate: inputs (1A/1B/2A/2B) accept logic signals, and outputs (1Y/2Y) drive loads. It lacks bus-hold, direction control, or tri-state capability. Bidirectional data transfer requires external transceivers or dedicated bus switches-not logic gates.

Can I use 74AUP2G08GT,115 with 5 V inputs?

No. Inputs tolerate up to 3.6 V absolute maximum, regardless of VCC. Applying 5 V violates Absolute Maximum Ratings and risks permanent damage. For 5 V interfacing, use a level translator like NX3LV08 or add external resistive divider with current limiting.

Is the XSON8 package (SOT833-1) reflow-compatible with standard lead-free profiles?

Yes. SOT833-1 is qualified for IPC/JEDEC J-STD-020 moisture sensitivity level 1 (MSL-1) and withstands peak reflow temperatures up to 260 °C. Ensure board layout follows Nexperia's recommended pad geometry (0.32 mm × 0.40 mm lands, 0.15 mm solder mask opening) for void-free solder joints.

How does IOFF behave when VCC = 0.1 V instead of 0 V?

At VCC = 0.1 V, IOFF leakage remains within ±0.75 μA (per datasheet Table 7, Tamb = –40 °C to +125 °C), because ΔIOFF adds only ±0.75 μA maximum across VCC = 0–0.2 V. Output remains effectively disabled, preserving system isolation during brown-out conditions.