NXP Semiconductors 74AUP2G125GM,125
- Part No.:
- 74AUP2G125GM,125
- Manufacturer:
- NXP Semiconductors
- Package:
- 8-XFQFN Exposed Pad
- Datasheet:
-
74AUP2G125GM,125.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 8XQFN
- Quantity:
- Payment:

- Shipping:

Inventory:108,000
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Product details
Overview
74AUP2G125GM,125 from Nexperia is a dual 3-state buffer/line driver with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ICC ≤ 0.9 μA (max), tpd ≤ 3.1 ns at 3.3 V/CL=5 pF, and IOFF-enabled partial power-down protection. It serves as a low-power signal routing and bus isolation device in space-constrained portable and battery-powered logic interfaces.
For engineers reviewing the 74AUP2G125GM,125 datasheet, 74AUP2G125GM,125 pinout, 74AUP2G125GM,125 application, or 74AUP2G125GM,125 equivalent, this page provides verified functional identity, validated XQFN8 pin mapping, confirmed -40 °C to +125 °C operation, and real-world substitution guidance for dual-buffer replacement in low-voltage I/O expansion designs.
Technical Context
The device implements two independent non-inverting buffers, each with active-low 3-state output enable (nOE) control and Schmitt-trigger input thresholds for noise immunity on slow-rising signals. Its IOFF circuitry actively disables outputs during VCC = 0 V, blocking backflow current and enabling hot-swap compatibility.
Designed for ultra-low static and dynamic power, it meets JEDEC standards JESD8-12 through JESD8-B across five voltage bands and supports ESD robustness per JS-001 Class 3A (≥5000 V HBM) and JS-002 Class C3 (≥1000 V CDM).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - enables direct interface with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Max ICC (Static) | 0.9 μA at 3.6 V - ensures sub-1 μA quiescent draw for always-on battery-backed subsystems. |
| tpd (VCC = 3.3 V, CL = 5 pF) | 3.1 ns max - supports >100 MHz data rates in short-trace point-to-point buffering. |
| IOFF Leakage (VCC = 0 V) | ±0.75 μA - prevents damaging back-current when powered down while system buses remain live. |
| Input Thresholds | VIL ≤ 0.3 × VCC, VIH ≥ 0.65 × VCC - provides hysteresis and noise margin up to 300 mV at 1.8 V. |
| Operating Temperature | -40 °C to +125 °C - qualified for under-hood automotive, industrial PLC, and high-reliability embedded control. |
| ESD Rating | HBM ≥ 5000 V, CDM ≥ 1000 V - exceeds IEC 61000-4-2 Level 4 for handling in unshielded assembly environments. |
Pinout & Package
XQFN8 package (SOT902-2): plastic ultra-thin quad flat no-lead, 1.6 × 1.6 × 0.55 mm body, 0.4 mm pitch, wettable flank terminals, exposed thermal pad.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1OE | Active-low enable for Buffer 1 - drives 1Y high-impedance when HIGH; requires pull-up for default disable. |
| 2 | 1A | Data input for Buffer 1 - Schmitt-triggered to tolerate slow edges and reject noise below hysteresis threshold. |
| 3 | 2Y | Output for Buffer 2 - 3-state capable; sinks/supplies ±20 mA; compatible with 5 pF–30 pF loads. |
| 4 | GND | Digital ground reference - must be low-inductance connection to minimize switching noise coupling. |
| 5 | 2A | Data input for Buffer 2 - electrically identical to 1A; supports independent asynchronous signal conditioning. |
| 6 | 2OE | Active-low enable for Buffer 2 - fully independent of 1OE; enables asymmetric bus gating. |
| 7 | 1Y | Output for Buffer 1 - matches 2Y drive strength and timing; supports bidirectional bus arbitration when paired. |
| 8 | VCC | Power supply - decoupling capacitor (100 nF ceramic) required within 3 mm for stable high-speed operation. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low ICC | 0.9 μA max across full VCC range - extends battery life in IoT sensor nodes and wearables. |
| IOFF Power-Down Protection | Blocks reverse current flow when VCC = 0 V - eliminates need for external isolation diodes in mixed-supply systems. |
| Schmitt-Trigger Inputs | Hysteresis ≥ 150 mV at 1.8 V - rejects EMI and contact bounce in mechanical switch interfaces and noisy PCB traces. |
| Overvoltage-Tolerant Inputs | Accepts up to 3.6 V regardless of VCC - allows safe interfacing with higher-voltage peripherals without clamping diodes. |
| Thermal-Enhanced XQFN8 | RθJA = 190 K/W - sustains continuous operation at +125 °C ambient in sealed enclosures with minimal airflow. |
Applications
| USB-C Port Multiplexing | Automotive Body Control Module |
|---|---|
Use Scenario: Isolating USB 2.0 D+/D− lines between host controller and alternate mode peripherals during reconfiguration. IC Role / Device Role / Timing Role: Dual 3-state buffer enabling/disabling differential pair paths under firmware control with <3.1 ns propagation delay. Use Value: Prevents signal contention during hot-plug events; Schmitt inputs suppress noise from cable insertion transients. | Use Scenario: Level-shifting and isolating LIN bus wake-up signals between 3.3 V microcontroller GPIO and 12 V vehicle battery domain. IC Role / Device Role / Timing Role: Buffering and enabling LIN TX/RX lines with IOFF protection during MCU sleep states. Use Value: Eliminates backfeed into MCU I/O pins during 12 V battery surge events; operates reliably at -40 °C to +125 °C. |
| Industrial Sensor Hub Interface | Portable Medical Device Data Acquisition |
Use Scenario: Aggregating analog sensor outputs (via ADC) onto shared SPI bus while preventing cross-talk between channels. IC Role / Device Role / Timing Role: Enabling/disabling individual sensor ADC output drivers using independent OE controls. Use Value: Reduces standby power by >95% vs. always-on buffers; 0.8 V minimum VCC supports energy-harvesting supply rails. | Use Scenario: Isolating ECG front-end amplifier outputs from low-power ARM Cortex-M0+ processor during deep-sleep cycles. IC Role / Device Role / Timing Role: Gatekeeper for biopotential signal path, asserting high-Z state during processor sleep to minimize leakage. Use Value: Achieves <1 μA total system sleep current; Schmitt inputs reject 50/60 Hz mains pickup on unshielded traces. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74AUP2G125DSFR | Same AUP family, identical electrical specs, but in USON8 (SOT-1202) package - 1.5 × 1.5 × 0.5 mm, no exposed pad. | Lacks thermal pad; RθJA ≈ 230 K/W - unsuitable for sustained +125 °C operation with >1 MHz switching. | Select when board area is tighter than thermal budget; verify layout derating for continuous 125 °C use. |
| 74LVC2G125GW,125 | Higher ICC (4 μA max), no IOFF, narrower VCC range (1.65 V–5.5 V), no Schmitt inputs. | Cannot safely power-down in mixed-supply systems; susceptible to noise on slow edges; incompatible with sub-1.65 V rails. | Choose only if cost is primary constraint and system uses fixed 3.3 V supply with clean, fast-rising signals. |
Compared with SN74AUP2G125DSFR and 74LVC2G125GW,125, the 74AUP2G125GM,125 uniquely combines sub-1 μA ICC, IOFF, Schmitt inputs, and thermal-enhanced XQFN8 - making it the sole option for battery-critical, hot-swap-safe, and wide-VCC industrial designs.
Availability
74AUP2G125GM,125 is available at Aetrix Electronics and suitable for USB-C port multiplexing, automotive body control modules, industrial sensor hubs, and portable medical device data acquisition requiring stable component supply across extended temperature ranges.
Supply support for 74AUP2G125GM,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert specializing in high-performance, energy-efficient logic, discrete, and MOSFET solutions, with manufacturing rooted in process innovation and automotive-grade reliability.
The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and thermally constrained applications where nanowatt static power, wide-VCC compatibility, and robust IOFF behavior are mandatory design requirements.
FAQ
What is the maximum output drive capability of 74AUP2G125GM,125?
The device delivers ±20 mA output current per channel at VCC = 3.3 V, with VOL ≤ 0.45 V and VOH ≥ 2.55 V under those conditions. Drive strength scales with supply voltage - at 1.8 V, it sources/sinks ~10 mA while maintaining rail-compatible logic levels. This enables direct interface with standard CMOS loads without external buffers.
Does 74AUP2G125GM,125 require external pull-up resistors on its OE pins?
Yes - because 1OE and 2OE are active-low inputs with no internal pull-ups, external 10 kΩ to VCC pull-up resistors are required to ensure defined HIGH state (and thus 3-state output) during power-up or floating conditions. This prevents unintended output activation that could cause bus contention in multi-driver systems.
Can 74AUP2G125GM,125 operate with VCC = 0 V while inputs are driven?
Yes - the IOFF circuitry actively disables both outputs and blocks current flow when VCC = 0 V, even if inputs are biased to 3.6 V. Input clamping current remains within ±50 mA limits, and IOFF leakage is specified at ±0.75 μA. This enables true partial power-down in systems where logic rails are sequenced independently.
Is the XQFN8 (SOT902-2) package RoHS and REACH compliant?
Yes - the 74AUP2G125GM,125 in XQFN8 packaging meets RoHS Directive 2011/65/EU (Pb-free, Cd-free, Hg-free, Cr⁶⁺-free, PBB/PBDE-free) and REACH Regulation (EC) No. 1907/2006, including SVHC screening. Full compliance documentation, including material declarations and test reports, is available upon request from Nexperia's official portal.
74AUP2G125GM,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 8-XFQFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XQFN (1.6x1.6)
74AUP2G125GM,125 FAQ
1.How can I place an order for 74AUP2G125GM,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G125GM,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G125GM,125 reliable?
The price and inventory of 74AUP2G125GM,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G125GM,125 is usually 5 days.
3.What payment methods are accepted for 74AUP2G125GM,125?
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4.How is shipping managed for 74AUP2G125GM,125?
74AUP2G125GM,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP2G125GM,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G125GM,125?
For technical support, including 74AUP2G125GM,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G125GM,125 requirements.
6.How does Aetrix verify that 74AUP2G125GM,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G125GM,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G125GM,125 meets industry standards.
7.What is the process for return or replacement of 74AUP2G125GM,125?
All 74AUP2G125GM,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G125GM,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G125GM,125 part is unused and in its original packaging.
Return procedure for 74AUP2G125GM,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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