Nexperia USA Inc. 74AUP2G125GN,115

Overview

74AUP2G125GN,115 from Nexperia is a dual 3-state buffer/line driver with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ICC ≤ 1.4 μA (max at −40 °C to +125 °C), tpd ≤ 4.4 ns (VCC = 3.0–3.6 V, CL = 5 pF), and IOFF-enabled partial power-down protection. It serves in low-power I/O expansion, voltage-level translation, and bus isolation in portable and industrial control systems.

For engineers reviewing the 74AUP2G125GN,115 datasheet, 74AUP2G125GN,115 pinout, 74AUP2G125GN,115 application, or 74AUP2G125GN,115 equivalent, key selection criteria include ultra-low static current, guaranteed 3-state output disable under VCC = 0 V, Schmitt-trigger noise immunity, and XSON8 (SOT1116) package compatibility with high-density PCB layouts.

Technical Context

This device implements two independent non-inverting buffers, each with active-low 3-state enable (nOE), enabling bidirectional bus control without external logic. All inputs feature Schmitt-trigger thresholds-VIH ≥ 0.70×VCC and VIL ≤ 0.30×VCC at VCC = 0.8 V-ensuring robust operation with slow-rising signals.

The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA (max), satisfying JEDEC JESD78B Class II latch-up immunity (>100 mA). Dynamic performance is characterized up to 30 pF load, with propagation delay scaling predictably with VCC and CL per Table 8.

Key Specifications

Pinout & Package

XSON8 package (SOT1116): extremely thin small outline, no leads, 8-terminal, 1.2 mm × 1.0 mm × 0.35 mm body, wettable flank compatible.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual 3-state buffer applications.

Compared with 74LVC2G125GW,125 and SN74AUP2G125DSFR, the 74AUP2G125GN,115 uniquely combines sub-μA static current, IOFF, and Schmitt-trigger inputs in the smallest XSON8 footprint (1.2 × 1.0 mm), making it optimal for space- and power-constrained edge nodes where signal integrity and fail-safe shutdown are critical.

Availability

74AUP2G125GN,115 is available at Aetrix Electronics and suitable for industrial sensor interface, portable device I/O expansion, automotive body control module, and industrial PLC digital input card applications requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP2G125GN,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-performance, energy-efficient logic, analog, and MOSFET solutions, with leadership in automotive-grade reliability and miniaturized packaging.

The 74AUP (Advanced Ultra-low Power) product line targets battery-powered and thermally constrained systems requiring sub-microamp quiescent current, robust noise immunity, and seamless voltage-domain bridging - especially in IoT edge nodes and automotive subsystems.

FAQ

What is the maximum allowable input voltage when VCC = 0 V?

The 74AUP2G125GN,115 supports overvoltage-tolerant inputs up to 3.6 V regardless of VCC level. When VCC = 0 V, VI may range from 0 V to 3.6 V without damage or excessive leakage, enabled by its IOFF circuitry that limits input current to ±0.75 μA (max) - critical for hot-plug and partial-power-down scenarios.

Does this device support true 1.2 V logic operation with guaranteed timing?

Yes. At VCC = 1.2 V (within 0.8–1.3 V JESD8-12 compliance), the device guarantees tpd ≤ 12.9 ns (CL = 5 pF, Tamb = −40 °C to +125 °C) and VIH ≥ 0.70×VCC (≥ 0.84 V), ensuring reliable operation in energy-harvesting and ultra-low-power microcontroller systems without timing margin loss.

How does the Schmitt-trigger input improve noise immunity compared to standard CMOS inputs?

Schmitt-trigger inputs provide hysteresis: VIH and VIL thresholds differ by ≥400 mV at VCC = 0.8 V. This prevents multiple output transitions caused by slow or noisy input edges - essential for interfacing with mechanical switches, long traces, or unshielded sensor lines in industrial settings where noise spikes exceed 200 mV.

Can both buffers be enabled simultaneously without crosstalk or increased supply current?

Yes. The two buffers are fully independent - 1A→1Y and 2A→2Y paths share only VCC and GND. Enabling both simultaneously increases ICC by ≤1 μA (ΔICC) versus single-buffer operation, per datasheet Table 7, and exhibits no measurable crosstalk (typical coupling < −50 dB) due to internal layout isolation and low-capacitance design (CI = 0.8 pF).