Nexperia USA Inc. 74AUP2G125GS,115
- Part No.:
- 74AUP2G125GS,115
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 8-XFDFN
- Datasheet:
-
74AUP2G125GS,115.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 8XSON
- Quantity:
- Payment:

- Shipping:

Inventory:9,398
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74AUP2G125GS,115 from Nexperia is a dual 3-state buffer/line driver with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ICC ≤ 1.4 μA (max at −40 °C to +125 °C), tpd ≤ 4.4 ns (VCC = 3.3 V, CL = 5 pF), and IOFF-enabled partial power-down protection. It serves in low-power I/O expansion, voltage-level translation, and bus isolation in portable and industrial control systems.
For engineers reviewing the 74AUP2G125GS,115 datasheet, 74AUP2G125GS,115 pinout, 74AUP2G125GS,115 application, or 74AUP2G125GS,115 equivalent, key selection criteria include ultra-low static current, guaranteed 3-state output disable under VCC = 0 V, Schmitt-trigger noise immunity, and XSON8 (SOT1203) package compatibility with high-density PCB layouts.
Technical Context
The device implements two independent non-inverting buffers, each with active-low 3-state enable (1OE, 2OE) and Schmitt-trigger input thresholds (VIH/VIL varying by VCC). Its IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V while inputs/outputs remain biased up to 3.6 V.
Dynamic performance is characterized by propagation delay (tpd), enable time (ten), and disable time (tdis), all specified across VCC = 0.8 V–3.6 V and temperature (−40 °C to +125 °C), with load capacitance dependencies (CL = 5–30 pF) explicitly tabulated for design margining.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - supports single-supply operation across 1.0 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains |
| Max ICC (−40 °C to +125 °C) | 1.4 μA - enables multi-year battery life in always-on sensor nodes and IoT endpoints |
| tpd (VCC = 3.3 V, CL = 5 pF) | 4.4 ns - sufficient for 100+ MHz data rates in low-latency serial interface buffering |
| IOFF Leakage (VCC = 0 V) | ±0.75 μA - prevents damaging back-current during hot-swap or partial system power-down |
| Input Threshold Hysteresis | Typical 100 mV - rejects noise on slow-rising/falling signals in noisy industrial environments |
| ESD Rating (HBM) | 5000 V - exceeds JEDEC JS-001 Class 3A, reducing need for external protection in handheld designs |
| Operating Temperature | −40 °C to +125 °C - qualified for under-hood automotive and industrial motor control applications |
Pinout & Package
XSON8 package (SOT1203): extremely thin, leadless, 1.35 mm × 1.0 mm × 0.35 mm body, 8-terminal surface-mount with exposed thermal pad (no internal thermal pad connection per datasheet).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1OE | Active-low enable for Buffer 1 - drives 1Y to high-impedance when HIGH |
| 2 | 1A | Data input for Buffer 1 - Schmitt-trigger input accepts slow edges without oscillation |
| 3 | 2Y | Data output for Buffer 2 - 3-state capable, compatible with shared bus topologies |
| 4 | GND | Ground reference - must be connected to PCB ground plane for EMI suppression |
| 5 | 2A | Data input for Buffer 2 - electrically isolated from 1A; supports dual independent channels |
| 6 | 1Y | Data output for Buffer 1 - driven LOW/HIGH or placed in high-Z per 1OE state |
| 7 | 2OE | Active-low enable for Buffer 2 - independent control allows staggered bus access |
| 8 | VCC | Power supply - decoupling capacitor (100 nF) required within 2 mm of pin for stable switching |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low static power | ICC ≤ 1.4 μA over full temp range - eliminates thermal derating concerns in sealed enclosures |
| IOFF partial power-down | Blocks backflow current at VCC = 0 V - enables safe insertion/removal in live backplanes |
| Schmitt-trigger inputs | Hysteresis ≥ 100 mV - tolerates >10 ns input rise/fall times without false triggering |
| Overvoltage-tolerant I/O | Inputs rated to 3.6 V regardless of VCC - simplifies level-shifting between 1.8 V and 3.3 V domains |
| JEDEC-compliant packaging | SOT1203 (XSON8) meets MO-252 footprint standards - ensures compatibility with automated optical inspection (AOI) |
Applications
| Industrial Sensor Interface | Portable Device Power Management |
|---|---|
Use Scenario: Isolating analog sensor outputs (e.g., thermistor, RTD) from noisy microcontroller ADC inputs in factory-floor PLC modules. IC Role / Device Role / Timing Role: Dual buffer provides noise-immune signal conditioning and bidirectional bus isolation during sleep/wake transitions. Use Value: Schmitt-trigger inputs reject EMI-induced glitches; IOFF prevents leakage current from draining backup batteries during extended shutdown. | Use Scenario: Enabling/disabling peripheral interfaces (e.g., SD card, display backlight) in wearable health monitors powered by coin-cell batteries. IC Role / Device Role / Timing Role: 3-state outputs gate power to peripherals; low ICC extends runtime between charges. Use Value: 1.4 μA max ICC reduces quiescent drain by >90% vs. standard AUP-series parts, adding weeks of shelf life. |
| Automotive Body Control Module | Low-Power IoT Gateway |
Use Scenario: Level-shifting and buffering LIN bus wake-up signals between 5 V legacy sensors and 3.3 V MCU in door module ECUs. IC Role / Device Role / Timing Role: Acts as voltage translator and signal conditioner; operates reliably at 125 °C ambient. Use Value: −40 °C to +125 °C rating eliminates derating; 3.6 V overvoltage tolerance avoids external clamping diodes. | Use Scenario: Managing SPI bus contention between LoRa transceiver, environmental sensor array, and host MCU in smart agriculture node. IC Role / Device Role / Timing Role: Dual buffer isolates transceiver from sensor reads; 3-state enables time-multiplexed bus sharing. Use Value: 4.4 ns tpd ensures timing margins for 20 MHz SPI clock; XSON8 footprint saves >40% board area vs. SOIC-8. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC2G125GS,132 | Higher ICC (max 40 μA at 3.3 V), no IOFF, VCC min = 1.65 V | Not suitable for battery-powered systems requiring true zero-VCC isolation | Select only if higher drive strength (24 mA) is needed and power-down isolation is unnecessary |
| SN74AUP2G125DSGR | Same electrical specs but VSSOP8 (SOT765-1) package; 2.3 mm body width | Requires larger PCB footprint and lacks thermal performance of XSON8 | Choose for hand-soldering or legacy board rework where XSON8 reflow is unavailable |
Compared with 74LVC2G125GS,132 and SN74AUP2G125DSGR, the 74AUP2G125GS,115 uniquely combines sub-μA ICC, IOFF protection, and 1.35 mm × 1.0 mm XSON8 packaging-enabling compact, battery-optimized designs where zero-VCC safety and minimal leakage are mandatory.
Availability
74AUP2G125GS,115 is available at Aetrix Electronics and suitable for industrial sensor interface, portable device power management, automotive body control, and low-power IoT gateway applications requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP2G125GS,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable discrete, logic, and MOSFET solutions for automotive, industrial, and consumer markets.
The 74AUP (Advanced Ultra-low Power) logic family targets battery-constrained and thermally sensitive applications, emphasizing sub-μA static current, wide VCC range, and robust IOFF behavior for modern embedded systems.
FAQ
What is the maximum allowable input voltage when VCC = 0 V?
The 74AUP2G125GS,115 supports overvoltage-tolerant inputs up to 3.6 V regardless of VCC state. When VCC = 0 V, VI may safely reach 3.6 V without damage or excessive leakage, enabling hot-plug capability in modular systems where subsystems power up asynchronously.
Does this device support mixed-voltage interfacing between 1.8 V and 3.3 V domains?
Yes. With VCC = 1.8 V, inputs accept VIH ≥ 1.17 V and VIL ≤ 0.54 V, while outputs drive VOH ≥ 1.6 V and VOL ≤ 0.35 V into 1.8 V loads. At VCC = 3.3 V, it drives 3.3 V logic levels and tolerates 1.8 V inputs directly-enabling seamless bidirectional level translation without external resistors.
How does the Schmitt-trigger input improve noise immunity in real-world layouts?
Schmitt-trigger inputs provide ≥100 mV hysteresis, rejecting noise spikes <100 mV and preventing multiple transitions on slow-rising signals (e.g., from RC-filtered sensors or long traces). This eliminates need for external RC filtering or software debouncing in industrial control inputs subject to EFT or conducted emissions.
Can the 74AUP2G125GS,115 be used in place of older 74AHC or 74LV families?
It can replace them in low-power applications but requires validation of timing margins: propagation delay is longer than 74AHC (e.g., 4.4 ns vs. ~3 ns at 3.3 V), and drive strength is lower (±20 mA vs. ±25 mA). Use only where ultra-low ICC and IOFF outweigh speed requirements-never as direct drop-in for high-speed clock distribution.
74AUP2G125GS,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 8-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XSON (1.35x1)
74AUP2G125GS,115 FAQ
1.How can I place an order for 74AUP2G125GS,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G125GS,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G125GS,115 reliable?
The price and inventory of 74AUP2G125GS,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G125GS,115 is usually 5 days.
3.What payment methods are accepted for 74AUP2G125GS,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP2G125GS,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP2G125GS,115?
74AUP2G125GS,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP2G125GS,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G125GS,115?
For technical support, including 74AUP2G125GS,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G125GS,115 requirements.
6.How does Aetrix verify that 74AUP2G125GS,115 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G125GS,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G125GS,115 meets industry standards.
7.What is the process for return or replacement of 74AUP2G125GS,115?
All 74AUP2G125GS,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G125GS,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G125GS,115 part is unused and in its original packaging.
Return procedure for 74AUP2G125GS,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74AUP2G125GS,115 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

