Nexperia USA Inc. 74AUP2G125GXX
- Part No.:
- 74AUP2G125GXX
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 8-XFDFN Exposed Pad
- Datasheet:
-
74AUP2G125GXX.pdf
- Description:
- IC BUF NON-INVERT 3.6V 8X2SON
- Quantity:
- Payment:

- Shipping:

Inventory:10,000
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Product details
Overview
74AUP2G125 from Nexperia is a dual CMOS buffer/line driver with independent 3-state outputs controlled by active-low enable inputs (1OE, 2OE), operating across 0.8 V to 3.6 V supply range. It features Schmitt-trigger inputs for noise immunity, IOFF circuitry for partial power-down protection, and ultra-low static current (≤1.4 μA at −40 °C to +125 °C). Used in voltage-level translation and bus isolation in portable IoT sensor nodes.
For engineers reviewing the 74AUP2G125 datasheet, 74AUP2G125 pinout, 74AUP2G125 application, or 74AUP2G125 equivalent, key selection criteria include its 0.8 V minimum VCC support, IOFF-enabled hot-swap capability, sub-1.5 μA ICC max over full temperature range, and compatibility with 1.2 V, 1.8 V, and 3.3 V logic domains.
Technical Context
This device implements two independent non-inverting buffers, each with dedicated output-enable control and Schmitt-trigger input thresholds-ensuring robust operation with slow-rising or noisy signals. The IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current during partial power-down sequences in multi-rail systems.
Dynamic performance is characterized by propagation delay as low as 1.4 ns (VCC = 3.3 V, CL = 5 pF) and disable time ≤3.9 ns under same conditions. Input and output capacitances are tightly controlled (CI ≤0.8 pF, CO ≤1.4 pF), minimizing loading on high-speed signal paths.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 0.8 V to 3.6 V - supports direct interface with 1.2 V, 1.8 V, and 3.3 V logic without level shifters |
| ICC (max) | 1.4 μA at −40 °C to +125 °C - enables multi-year battery life in always-on sensor edge nodes |
| tpd (max) | 4.4 ns at VCC = 3.3 V, CL = 5 pF - sufficient for ≤100 MHz data bus buffering |
| IOFF Leakage | ±0.75 μA at VCC = 0 V - prevents damaging back-current during hot insertion or rail sequencing |
| VIH/VIL Thresholds | VIL ≤0.3×VCC, VIH ≥0.7×VCC (at VCC = 1.4 V) - provides >400 mV noise margin in 1.2 V–1.8 V systems |
| ESD Rating | HBM >5000 V, CDM >1000 V - meets industrial IEC 61000-4-2 system-level ESD robustness requirements |
| Operating Temp | −40 °C to +125 °C - qualified for under-hood automotive and industrial motor control environments |
Pinout & Package
Available in five miniature packages: VSSOP8 (SOT765-1), XSON8 (SOT833-1, SOT1116, SOT1203), and thermal-enhanced X2SON8 (SOT1233-2). All variants are 8-terminal, no-lead or gull-wing, with pin 1 marked by index area or marking code location.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1OE, 2OE | Active-low output enable | Drives corresponding Y output to high-impedance state when HIGH; enables independent bus arbitration per channel |
| 1A, 2A | Data input | Schmitt-triggered inputs tolerate slow edges and reject noise up to 40% of VCC swing |
| 1Y, 2Y | Buffered output | Non-inverting, 3-state outputs support bidirectional bus sharing and load driving up to ±20 mA |
| VCC | Supply voltage | Single supply powers both channels; IOFF remains active even if VCC drops to 0 V |
| GND | Ground reference | Common return path for all inputs, outputs, and internal logic; decoupling required within 2 mm |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range | 0.8 V to 3.6 V enables single part to serve multiple voltage domains in mixed-supply SoC interfaces |
| IOFF circuitry | Prevents destructive back-current during power sequencing-critical for PCIe add-in cards and hot-pluggable modules |
| Schmitt-trigger inputs | Input hysteresis ≥150 mV at 1.2 V ensures reliable switching despite ringing or slow RC edges on PCB traces |
| Ultra-low ICC | ≤1.4 μA max over full temp range reduces quiescent power in always-on wake-up circuits and battery-backed memory buffers |
| Thermal-enhanced X2SON8 | SOT1233-2 package delivers 300 mW Ptot with 7.7 mW/K derating above 118 °C-suited for enclosed industrial enclosures |
Applications
| Industrial Sensor Hub | Automotive Body Control Module |
|---|---|
|
Use Scenario: Isolating I²C/SPI lines between 1.8 V MCU and 3.3 V analog front-end in a factory-floor vibration sensor node. IC Role / Device Role / Timing Role: Level-translating buffer with independent OE control per channel to prevent bus contention during firmware updates. Use Value: Eliminates need for discrete level shifters; IOFF protects 3.3 V domain when 1.8 V rail powers down first during sleep mode. |
Use Scenario: Driving LIN bus transceiver enable lines from a 5 V-tolerant 3.3 V microcontroller in door module electronics. IC Role / Device Role / Timing Role: Dual buffer with Schmitt-trigger inputs cleans noisy switch inputs before routing to MCU GPIOs. Use Value: Reduces false wake-ups from EMI; 125 °C rating ensures reliability near power window motor drivers. |
| Portable Medical Wearable | Smart Energy Meter Interface |
|
Use Scenario: Buffering ADC serial data lines between ultra-low-power 1.2 V SAR ADC and 1.8 V application processor. IC Role / Device Role / Timing Role: Low-capacitance (CI ≤0.8 pF) buffer preserves signal integrity on 10 cm flex PCB traces. Use Value: Enables 1.2 V operation without compromising timing margin-extends coin-cell battery life beyond 3 years. |
Use Scenario: Isolating RS-485 transceiver control signals from metering SoC during firmware OTA updates. IC Role / Device Role / Timing Role: 3-state outputs prevent bus conflicts while SoC reboots; IOFF blocks leakage into powered-down transceiver. Use Value: Meets IEC 62056-21 compliance for zero-fault communication handover during field upgrades. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G125DPWR | Wider VCC range (1.65 V–5.5 V); higher ICC (10 μA typ); no IOFF; no Schmitt inputs | Requires external pull-downs for floating inputs; unsuitable for partial power-down systems | Select only if 5 V tolerance is mandatory and power sequencing is not required |
| 74LVC2G126GW,125 | Inverting function; identical VCC/ICC/IOFF specs; same XSON8 footprint as 74AUP2G125GN/GS | Used where signal polarity inversion is acceptable (e.g., inverted reset distribution) | Drop-in replacement for inverting buffer needs-pin-compatible with GN/GS packages |
Compared with SN74LVC2G125DPWR and 74LVC2G126GW,125, the 74AUP2G125 uniquely combines sub-1.5 μA ICC, IOFF, and Schmitt inputs in a single 0.8 V–3.6 V device-making it the only choice for energy-constrained, multi-rail, noise-prone embedded interfaces.
Availability
74AUP2G125 is available at Aetrix Electronics and suitable for industrial sensor hubs, automotive body control modules, and portable medical wearables requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP2G125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable, and efficient logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.
The 74AUP (Advanced Ultra-low Power) product line targets battery-powered and thermally constrained applications, emphasizing minimal ICC, wide VCC flexibility, and robust IOFF behavior for safe multi-voltage system design.
FAQ
What is the maximum capacitive load the 74AUP2G125 can drive while maintaining specified tpd?
The datasheet specifies propagation delay (tpd) up to CL = 30 pF across all VCC and temperature ranges. At VCC = 3.3 V and Tamb = 25 °C, tpd remains ≤5.8 ns with 30 pF load. Driving >30 pF increases delay nonlinearly and may exceed timing budgets in high-speed interfaces-external series termination or buffer staging is recommended beyond this limit.
Can 74AUP2G125 be used with 5 V inputs when VCC = 3.3 V?
No. Inputs are overvoltage tolerant only up to 3.6 V, and absolute maximum VI is +4.6 V-but sustained 5 V input violates JEDEC JESD8-B compliance and risks latch-up or accelerated degradation. For 5 V-tolerant interfacing, use a dedicated level translator such as TXB0102 or SN74AVC2T244.
How does the IOFF feature behave when VCC ramps from 0 V to nominal?
IOFF activates immediately upon VCC dropping below ~0.2 V and remains active until VCC exceeds ~0.5 V. During ramp-up, outputs stay in high-impedance until VCC reaches functional threshold (~0.8 V), preventing glitching or contention. This behavior is verified per JESD78B Class II latch-up testing and guarantees safe hot-insertion.
Which package offers the best thermal performance for continuous 20 mA output loading?
The X2SON8 package (SOT1233-2) delivers highest thermal performance: Ptot = 300 mW at Tamb ≤118 °C, with 7.7 mW/K derating above that. Under 20 mA per output at VCC = 3.3 V, power dissipation is ~132 mW-well within derated limits up to +125 °C ambient, making it optimal for enclosed industrial drives or automotive junction boxes.
74AUP2G125GXX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 8-XFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-X2SON (1.35x0.8)
74AUP2G125GXX FAQ
1.How can I place an order for 74AUP2G125GXX through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G125GXX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G125GXX reliable?
The price and inventory of 74AUP2G125GXX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G125GXX is usually 5 days.
3.What payment methods are accepted for 74AUP2G125GXX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP2G125GXX transactions.
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74AUP2G125GXX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP2G125GXX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G125GXX?
For technical support, including 74AUP2G125GXX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G125GXX requirements.
6.How does Aetrix verify that 74AUP2G125GXX is sourced from the original manufacturer or authorized distributors?
All 74AUP2G125GXX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G125GXX meets industry standards.
7.What is the process for return or replacement of 74AUP2G125GXX?
All 74AUP2G125GXX units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G125GXX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G125GXX part is unused and in its original packaging.
Return procedure for 74AUP2G125GXX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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