NXP Semiconductors 74AUP2G126GD,125
- Part No.:
- 74AUP2G126GD,125
- Manufacturer:
- NXP Semiconductors
- Package:
- 8-XFDFN
- Datasheet:
-
74AUP2G126GD,125.pdf
- Description:
- IC BUFFER/LINEDVR DUAL XSON8U
- Quantity:
- Payment:

- Shipping:

Inventory:75,000
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Product details
Overview
74AUP2G126GD,125 from Nexperia is a dual CMOS buffer/line driver with independent 3-state outputs controlled by active-HIGH output enable inputs (1OE, 2OE), operating across 0.8 V to 3.6 V supply range. It features Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and ultra-low static current (≤1.4 μA at −40 °C to +125 °C). Used in voltage-level translation and bus isolation in portable IoT sensor nodes.
For engineers reviewing the 74AUP2G126GD,125 datasheet, 74AUP2G126GD,125 pinout, 74AUP2G126GD,125 application, or 74AUP2G126GD,125 equivalent, key selection criteria include its 0.8 V minimum VCC support, sub-1.5 μA ICC max at full temperature range, IOFF-enabled backflow prevention during power sequencing, and compatibility with 1.2 V, 1.8 V, and 3.3 V logic domains.
Technical Context
This device implements two independent non-inverting buffers, each with dedicated output enable control and Schmitt-trigger input thresholds-enabling robust operation with slow-rising signals and high noise margin. The IOFF circuit actively disables outputs when VCC = 0 V, limiting reverse current to ±0.75 μA even with I/O pins biased up to 3.6 V.
Dynamic performance is characterized across four load capacitances (5–30 pF) and five VCC ranges (0.8 V to 3.6 V); propagation delay tpd reaches 1.4 ns (typ.) at 3.3 V/5 pF, while enable/disable times remain under 4.7 ns (max) over full temperature range. Input and output capacitances are tightly specified at CI = 0.9 pF and CO = 1.5–1.7 pF.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 0.8 V to 3.6 V - supports single-supply operation across 1.2 V, 1.8 V, and 3.3 V logic families without level shifters. |
| ICC (max) | 1.4 μA at −40 °C to +125 °C - enables multi-year battery life in always-on sensor interface circuits. |
| IOFF Leakage | ±0.75 μA at VCC = 0 V - prevents damaging backflow current during hot-swap or partial power-down sequences. |
| tpd (max) | 4.4 ns at VCC = 3.0–3.6 V, CL = 5 pF - sufficient for 100+ MHz data strobing in low-power microcontroller peripheral buses. |
| VIH/VIL Thresholds | VIL ≤ 0.3×VCC, VIH ≥ 0.7×VCC (at 1.4 V) - ensures reliable switching with noisy or slew-limited GPIO signals. |
| ESD Rating | HBM > 5000 V, CDM > 1000 V - meets industrial handling requirements without additional protection circuitry. |
| Operating Temp | −40 °C to +125 °C - qualified for under-hood automotive, industrial motor control, and outdoor edge-node deployments. |
Pinout & Package
XSON8 plastic extremely thin small outline package (no leads); 8-terminal surface-mount; body dimensions 1.2 mm × 1.0 mm × 0.35 mm (SOT1116).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1OE | Output enable input (Channel 1) | Active-HIGH control: drives 1Y to high-impedance when LOW; enables Schmitt-trigger input stage. |
| 1A | Data input (Channel 1) | Non-inverting buffer input with hysteresis; tolerant of slow edges and rail-to-rail voltage swings up to 3.6 V. |
| 1Y | Data output (Channel 1) | CMOS push-pull output capable of sourcing/sinking 4 mA at 3.0 V; supports 3.6 V-tolerant off-state. |
| GND | Ground reference | 0 V return path for all internal logic and I/O; must be low-inductance connection for noise immunity. |
| 2A | Data input (Channel 2) | Independent non-inverting input with identical Schmitt characteristics and voltage tolerance as 1A. |
| 2OE | Output enable input (Channel 2) | Independent active-HIGH control for 2Y; allows asymmetric channel enabling in multiplexed bus architectures. |
| 2Y | Data output (Channel 2) | Electrically isolated from 1Y; supports separate loading and timing; shares same VCC/GND rails. |
| VCC | Supply voltage | Single power rail for both channels; IOFF remains active even if VCC drops below 0.2 V. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low static power | ICC ≤ 1.4 μA over −40 °C to +125 °C - eliminates thermal derating concerns in sealed enclosures. |
| IOFF partial power-down | Blocks bidirectional current flow when VCC = 0 V - enables safe live insertion into powered backplanes. |
| Schmitt-trigger inputs | Hysteresis ≥ 0.3×VCC - rejects EMI-induced glitches on long PCB traces or flex cables. |
| Overvoltage-tolerant I/O | Inputs and outputs withstand 3.6 V regardless of VCC - simplifies mixed-voltage system interconnect. |
| Multiple compact packages | SOT1116 (1.2×1.0×0.35 mm) and SOT1203 (1.35×1.0×0.35 mm) - ideal for space-constrained wearables and modules. |
Applications
| Industrial Sensor Interface | Low-Power MCU Peripheral Bus |
|---|---|
|
Use Scenario: Isolating analog sensor ADC outputs from noisy digital MCU domains in factory-floor condition monitoring systems. IC Role / Device Role / Timing Role: Dual-channel level-shifting buffer with independent OE control, enabling time-multiplexed sampling of two sensors without cross-talk. Use Value: IOFF prevents sensor-side leakage when MCU enters deep sleep, extending battery life beyond 5 years in wireless vibration monitors. |
Use Scenario: Driving multiple SPI slave select lines from a single 3.3 V GPIO bank on an ARM Cortex-M0+ microcontroller. IC Role / Device Role / Timing Role: Non-inverting line driver with Schmitt inputs, ensuring clean transitions despite trace inductance and capacitive loading. Use Value: 1.4 ns typical tpd at 3.3 V/5 pF guarantees setup/hold compliance for 20 MHz SPI clocking with zero added jitter. |
| Automotive Body Control Module | Portable Medical Device Data Hub |
|
Use Scenario: Interfacing 1.2 V CAN transceiver status signals to a 3.3 V microcontroller in door module ECUs. IC Role / Device Role / Timing Role: Voltage-tolerant buffer enabling direct connection between disparate supply domains without external resistors or translators. Use Value: 3.6 V-tolerant I/O eliminates level-shifter ICs, reducing BOM count and PCB area by 32% in ASIL-B compliant designs. |
Use Scenario: Multiplexing ECG electrode signals into a low-noise analog front-end while maintaining digital isolation from Bluetooth radio subsystem. IC Role / Device Role / Timing Role: Dual 3-state buffer used as signal gate, enabling dynamic reconfiguration of electrode routing paths via firmware. Use Value: Sub-1.5 μA ICC ensures <10 nA contribution to total system leakage, critical for >7-day continuous ECG recording on coin-cell power. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G126DPWR | Wider VCC range (1.65–5.5 V); higher ICC (10 μA typ.); no IOFF; no Schmitt inputs. | Requires external pull-ups for 1.2 V/1.8 V use; unsuitable for partial power-down scenarios. | Select when interfacing legacy 5 V peripherals and thermal budget allows higher static draw. |
| 74LVC2G126GM,132 | Same XSON8 footprint (SOT886); identical IOFF and Schmitt features; slightly higher tpd (5.2 ns max at 3.3 V). | Compatible pinout and function but rated only to +85 °C ambient; lower thermal performance in enclosed housings. | Choose for cost-sensitive consumer designs where extended temperature range is not required. |
Compared with SN74LVC2G126DPWR and 74LVC2G126GM,132, the 74AUP2G126GD,125 uniquely delivers sub-1.5 μA ICC at +125 °C while retaining IOFF and Schmitt functionality-making it the only option for thermally constrained, battery-powered, and automotive-grade dual-buffer applications.
Availability
74AUP2G126GD,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, low-power MCU peripheral buses, automotive body control modules, and portable medical device data hubs requiring stable component supply across extended temperature and voltage ranges.
Supply support for 74AUP2G126GD,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable, and energy-efficient components for automotive, industrial, mobile, and computing markets.
The 74AUP (Advanced Ultra-low Power) logic family targets battery-operated and thermally constrained systems, emphasizing minimal ICC, wide VCC scalability, and robustness in mixed-voltage environments.
FAQ
Does 74AUP2G126GD,125 support true bidirectional I/O?
No. It is a unidirectional dual buffer with non-inverting data paths (1A→1Y, 2A→2Y). Each channel has independent active-HIGH output enable (1OE, 2OE) but no automatic direction control or bus transceiver capability. Direction must be managed externally via OE timing.
Can 74AUP2G126GD,125 be used with 0.8 V microcontrollers?
Yes. Its guaranteed operation down to 0.8 V VCC, combined with Schmitt-trigger inputs and VIH/VIL thresholds referenced to VCC, makes it fully compatible with sub-1.0 V logic families such as certain ultra-low-power RISC-V cores and energy-harvesting SoCs.
What is the maximum capacitive load for stable 3.3 V operation?
The device is characterized up to 30 pF load capacitance. At VCC = 3.3 V and CL = 30 pF, tpd remains ≤8.3 ns and tdis ≤12.0 ns across −40 °C to +125 °C, confirming stability with typical PCB trace + connector + receiver input capacitance.
Is the SOT1116 (XSON8) package lead-free and RoHS-compliant?
Yes. The 74AUP2G126GD,125 in SOT1116 packaging uses lead-free matte tin terminal finish and complies with RoHS Directive 2011/65/EU and REACH SVHC regulations, with full material declarations available from Nexperia's product change notifications.
74AUP2G126GD,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 8-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XSON (2x3)
74AUP2G126GD,125 FAQ
1.How can I place an order for 74AUP2G126GD,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G126GD,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G126GD,125 reliable?
The price and inventory of 74AUP2G126GD,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G126GD,125 is usually 5 days.
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5.How can I obtain technical support or documentation for 74AUP2G126GD,125?
For technical support, including 74AUP2G126GD,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G126GD,125 requirements.
6.How does Aetrix verify that 74AUP2G126GD,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G126GD,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G126GD,125 meets industry standards.
7.What is the process for return or replacement of 74AUP2G126GD,125?
All 74AUP2G126GD,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G126GD,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G126GD,125 part is unused and in its original packaging.
Return procedure for 74AUP2G126GD,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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