Nexperia USA Inc. 74AUP2G126GM,125
- Part No.:
- 74AUP2G126GM,125
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 8-XFQFN Exposed Pad
- Datasheet:
-
74AUP2G126GM,125.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 8XQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74AUP2G126GM,125 from Nexperia is a dual 3-state buffer/line driver with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ultra-low static current (≤1.4 μA at −40 °C to +125 °C), IOFF-enabled partial power-down protection, and <10 % VCC overshoot/undershoot - deployed in low-power sensor interface and battery-powered I/O expansion circuits.
For engineers reviewing the 74AUP2G126GM,125 datasheet, 74AUP2G126GM,125 pinout, 74AUP2G126GM,125 application, or 74AUP2G126GM,125 equivalent, key selection criteria include its dual-channel 3-state drive capability, guaranteed operation down to 0.8 V, IOFF leakage ≤±0.75 μA at VCC = 0 V, Schmitt-trigger noise immunity, and compatibility with 1.2 V, 1.8 V, and 3.3 V logic domains.
Technical Context
This device implements two independent non-inverting buffers, each with active-HIGH output enable (1OE, 2OE) controlling high-impedance (Z) output states. Its Schmitt-trigger inputs tolerate slow-rising/falling signals and provide hysteresis of typically 0.1 × VCC, enhancing noise rejection in noisy environments.
The IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current up to ±0.75 μA - critical for hot-swap and multi-rail systems. All inputs tolerate overvoltage up to 3.6 V regardless of VCC, enabling level-shifting between disparate supply domains without external components.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - supports single-supply operation across 1.2 V, 1.8 V, and 3.3 V logic families without level shifters. |
| Max ICC (VCC = 0.8–3.6 V) | 1.4 μA at −40 °C to +125 °C - enables >10-year battery life in always-on IoT sensor nodes. |
| IOFF Leakage (VCC = 0 V) | ±0.75 μA - prevents damaging backfeed current during partial power-down in mixed-voltage systems. |
| Propagation Delay (CL = 15 pF, VCC = 3.3 V) | 4.4 ns - ensures timing-critical signal routing in high-speed microcontroller GPIO expansion. |
| Input Hysteresis (Schmitt) | Typ. 0.1 × VCC - rejects noise spikes up to 330 mV on 3.3 V inputs, eliminating external RC filtering. |
| Overvoltage Tolerance | Inputs rated to 3.6 V independent of VCC - allows safe interfacing with 3.3 V peripherals while powered from 1.8 V. |
| ESD Rating (HBM) | 5000 V - exceeds JEDEC JS-001 Class 3A, reducing board-level ESD protection component count. |
Pinout & Package
XQFN8 package (SOT902-2): plastic ultra-thin quad flat no-lead, 8-terminal, body size 1.35 mm × 1.35 mm × 0.45 mm, exposed thermal pad, lead pitch 0.4 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1OE | Active-HIGH output enable for Channel 1 - drives 1Y to high-Z when LOW; ties directly to MCU GPIO for dynamic bus control. |
| 2 | 1A | Data input for Channel 1 - accepts Schmitt-triggered signals with hysteresis, tolerant of slow edges and noise. |
| 3 | 2Y | Data output for Channel 2 - provides rail-to-rail CMOS drive into 50 pF loads with <10 % VCC ringing. |
| 4 | GND | Digital ground reference - must be connected to system ground plane; shared with thermal pad for thermal dissipation. |
| 5 | 2A | Data input for Channel 2 - electrically identical to 1A; supports independent signal conditioning per channel. |
| 6 | 1Y | Data output for Channel 1 - delivers same drive strength and timing as 2Y; enables dual parallel data paths. |
| 7 | 2OE | Active-HIGH output enable for Channel 2 - independently controls 2Y, enabling selective channel isolation. |
| 8 | VCC | Supply voltage input - decoupling capacitor (100 nF) required within 2 mm for stable low-noise operation. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low power consumption | ICC ≤ 1.4 μA across full temperature range - reduces quiescent load in always-on wearable sensors. |
| IOFF partial power-down | Blocks backflow current at VCC = 0 V - eliminates need for external isolation switches in hot-plug modules. |
| Schmitt-trigger inputs | Hysteresis ≥ 0.1 × VCC - rejects EMI-induced glitches on long PCB traces without added filtering components. |
| Overvoltage-tolerant inputs | Rated to 3.6 V regardless of VCC - enables direct connection to 3.3 V buses while operating from 1.2 V supply. |
| Wide temperature range | Specified from −40 °C to +125 °C - qualified for under-hood automotive and industrial motor control applications. |
Applications
| Industrial Sensor Interface | Low-Power Wearable Hub |
|---|---|
|
Use Scenario: Interfacing analog sensor outputs (e.g., thermistor, pressure transducer) to a 1.8 V microcontroller ADC input with long trace runs. IC Role / Device Role / Timing Role: Dual buffer isolates noisy analog domain from digital domain; Schmitt inputs reject coupling noise on PCB traces. Use Value: Eliminates external RC filters and level shifters, reducing BOM count by two components per channel while maintaining signal integrity. |
Use Scenario: Expanding GPIO count on a coin-cell-powered fitness tracker MCU with strict 5 μA sleep budget. IC Role / Device Role / Timing Role: 3-state outputs enable time-multiplexed peripheral access; IOFF prevents battery drain during MCU deep-sleep mode. Use Value: Achieves sub-μA effective standby current per channel, extending battery life beyond 12 months without compromising I/O flexibility. |
| Automotive Body Control Module | USB-C Power Delivery Negotiation |
|
Use Scenario: Level-shifting and buffering I²C signals between 3.3 V infotainment SoC and 5 V lighting controller in ambient temperature up to 105 °C. IC Role / Device Role / Timing Role: Input overvoltage tolerance allows direct 3.3 V I²C SDA/SCL connection to 5 V domain; 125 °C rating ensures reliability. Use Value: Removes need for discrete MOSFET level shifters, cutting layout area by 30 % and improving I²C rise-time consistency. |
Use Scenario: Isolating CC1/CC2 configuration channel lines between USB-C port controller (3.3 V) and legacy 5 V PD policy engine. IC Role / Device Role / Timing Role: Dual independent buffers with separate OE pins support asymmetric enable sequencing required for USB-C spec compliance. Use Value: Guarantees <4.4 ns propagation delay at 3.3 V, meeting USB-C 2.1 timing margin for robust PD negotiation under worst-case voltage/temp conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G126DCUR | Wider VCC range (1.65–5.5 V); higher ICC (10 μA typ); no IOFF; no Schmitt inputs | Requires external pull-ups for open-drain compatibility; unsuitable for sub-1.65 V operation or hot-swap isolation | Select when interfacing 5 V peripherals and higher speed (>10 ns) is acceptable; avoid for battery-critical or 0.8–1.2 V systems. |
| 74LVC2G126GM,125 | Same footprint (XQFN8); VCC = 1.65–5.5 V; ICC = 10 μA max; lacks IOFF and Schmitt inputs | Cannot support partial power-down or slow/noisy inputs; requires external hysteresis or clamping for marginal signals | Choose only if existing design uses LVC family and operates strictly above 1.65 V; not drop-in compatible for AUP's low-VCC or IOFF use cases. |
Compared with SN74LVC2G126DCUR and 74LVC2G126GM,125, the 74AUP2G126GM,125 uniquely enables sub-1 V operation, eliminates backfeed risk via IOFF, and removes external noise filtering needs through integrated Schmitt triggers - making it irreplaceable in ultra-low-power, mixed-voltage, or EMI-prone designs.
Availability
74AUP2G126GM,125 is available at Aetrix Electronics and suitable for industrial sensor interface, low-power wearable hubs, automotive body control modules, and USB-C power delivery negotiation requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP2G126GM,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable, and energy-efficient components for automotive, industrial, mobile, and computing applications - with leadership in logic, discretes, and MOSFETs.
The 74AUP (Advanced Ultra-low Power) product line targets battery-powered and energy-sensitive systems, emphasizing sub-1 V operation, nanoamp ICC, and robust IOFF behavior - designed specifically for next-generation IoT edge nodes and portable electronics.
FAQ
What is the maximum allowable input voltage when VCC = 0 V?
The 74AUP2G126GM,125 inputs are overvoltage tolerant up to 3.6 V regardless of VCC state. When VCC = 0 V, VI(max) remains +3.6 V, and IOFF limits input-to-output leakage to ±0.75 μA - enabling safe "live insertion" into powered-backplane systems without damage or bus contention.
Does this device support true bidirectional data flow?
No. The 74AUP2G126GM,125 is a unidirectional non-inverting buffer with fixed input (nA) and output (nY) terminals. It does not implement bus transceiver functionality or automatic direction control. Bidirectional operation requires external control logic or a dedicated transceiver IC such as the 74AUP2G241.
Can both output enable pins be tied together?
Yes - 1OE and 2OE may be paralleled to a single control signal for simultaneous channel enable/disable. Electrical characteristics (VIH/VIL, input capacitance) remain valid under this configuration, and no additional current loading or timing degradation occurs per the datasheet's functional description and pin description tables.
Is the thermal pad (pin 4) required to be soldered?
Yes. The exposed thermal pad (connected internally to GND) must be soldered to a PCB thermal land for mechanical stability and thermal performance. Datasheet section 12 specifies SOT902-2 (XQFN8) mounting requirements, and omitting pad soldering risks exceeding junction temperature limits under sustained 20 mA output loading, especially at +125 °C ambient.
74AUP2G126GM,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 8-XFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XQFN (1.6x1.6)
74AUP2G126GM,125 FAQ
1.How can I place an order for 74AUP2G126GM,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G126GM,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G126GM,125 reliable?
The price and inventory of 74AUP2G126GM,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G126GM,125 is usually 5 days.
3.What payment methods are accepted for 74AUP2G126GM,125?
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4.How is shipping managed for 74AUP2G126GM,125?
74AUP2G126GM,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP2G126GM,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G126GM,125?
For technical support, including 74AUP2G126GM,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G126GM,125 requirements.
6.How does Aetrix verify that 74AUP2G126GM,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G126GM,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G126GM,125 meets industry standards.
7.What is the process for return or replacement of 74AUP2G126GM,125?
All 74AUP2G126GM,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G126GM,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G126GM,125 part is unused and in its original packaging.
Return procedure for 74AUP2G126GM,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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