Nexperia USA Inc. 74AUP2G126GN,115
- Part No.:
- 74AUP2G126GN,115
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 8-XFDFN
- Datasheet:
-
74AUP2G126GN,115.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 8XSON
- Quantity:
- Payment:

- Shipping:

Inventory:70,400
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Product details
Overview
74AUP2G126GN,115 from Nexperia is a dual 3-state buffer/line driver with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply range, delivering ultra-low static current (≤1.4 μA at −40 °C to +125 °C), IOFF-enabled partial power-down protection, and propagation delay as low as 1.4 ns at 3.3 V. It serves in voltage-level translation and bus isolation for low-power portable and industrial microcontroller peripheral interfaces.
For engineers reviewing the 74AUP2G126GN,115 datasheet, 74AUP2G126GN,115 pinout, 74AUP2G126GN,115 application, or 74AUP2G126GN,115 equivalent, this device is selected for its sub-1.5 μA ICC, guaranteed operation up to +125 °C, IOFF backflow prevention, Schmitt-trigger noise immunity, and XSON8 footprint compatibility with space-constrained PCB layouts.
Technical Context
The 74AUP2G126GN implements two independent non-inverting buffers, each with active-HIGH output enable (1OE, 2OE) controlling high-impedance (Z) state on respective outputs (1Y, 2Y). Inputs feature Schmitt-trigger action with hysteresis ≥0.3 V at VCC = 3.3 V, enabling robust operation with slow-rising signals.
Its IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA, and it complies with JEDEC standards JESD8-12 through JESD8C across five voltage bands. The device supports dynamic loading up to 30 pF with tpd ≤6.1 ns at 3.3 V and CL = 30 pF.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - Enables direct interface with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Max ICC (−40 °C to +125 °C) | 1.4 μA - Ensures battery-powered systems retain >10-year shelf life with minimal quiescent drain. |
| IOFF Leakage (VCC = 0 V) | ±0.75 μA - Prevents damaging back-current into powered subsystems during hot-swap or partial power-down sequences. |
| tpd @ VCC = 3.3 V, CL = 5 pF | 1.4 ns - Supports signal integrity in high-speed digital control paths up to ~350 MHz toggle rate. |
| Input Hysteresis (Schmitt) | ≥0.3 V at VCC = 3.3 V - Rejects noise spikes ≤300 mV on slow GPIO lines (e.g., pushbutton, sensor outputs). |
| Operating Temperature | −40 °C to +125 °C - Qualified for under-hood automotive, industrial motor drives, and outdoor IoT edge nodes. |
| ESD Rating (HBM) | 5000 V - Reduces need for external ESD protection on board-level I/O traces. |
Pinout & Package
XSON8 package (SOT1116): extremely thin small outline, no leads, 8-terminal, body size 1.2 mm × 1.0 mm × 0.35 mm, thermal padless, pin 1 marked by lower-left corner notch below "pN" marking.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1OE | Active-HIGH output enable for Channel 1 - Driven HIGH to enable 1Y; LOW or floating places 1Y in high-Z. |
| 2 | 1A | Data input for Channel 1 - Schmitt-triggered; accepts 0–3.6 V regardless of VCC, enabling mixed-voltage interfacing. |
| 3 | 2Y | Data output for Channel 2 - 3-state capable; driven only when 2OE = HIGH; otherwise high-impedance. |
| 4 | GND | Ground reference - Must be connected directly to system ground plane; no shared return with noisy power rails. |
| 5 | 2A | Data input for Channel 2 - Electrically identical to 1A; supports independent dual-channel buffering. |
| 6 | 1Y | Data output for Channel 1 - Non-inverting; output swing rail-to-rail within VCC tolerance (VOH ≥2.3 V, VOL ≤0.5 V @ 3.3 V). |
| 7 | 2OE | Active-HIGH output enable for Channel 2 - Independent control allows time-multiplexed bus sharing between two peripherals. |
| 8 | VCC | Supply voltage input - Decoupling capacitor (100 nF ceramic) required within 2 mm of pin for stable switching performance. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Enables reliable detection of slow or noisy signals (e.g., mechanical switches, analog sensor thresholds) without external hysteresis circuitry. |
| IOFF partial power-down | Prevents destructive back-current flow when VCC is off but I/O pins remain biased - critical for hot-pluggable modules and modular systems. |
| Ultra-low ICC (≤1.4 μA) | Reduces system-level standby power by >95% versus standard AHC/AHCT logic, extending battery life in always-on sensors and wearables. |
| Overvoltage-tolerant inputs | Accepts up to 3.6 V input regardless of VCC setting - simplifies interconnection between 1.8 V MCU and 3.3 V peripherals without level translators. |
| JEDEC-compliant voltage bands | Validated across five industry-standard supply ranges (0.8–1.3 V, 0.9–1.65 V, etc.), ensuring interoperability in multi-rail SoC designs. |
Applications
| Industrial Sensor Interface | Automotive Body Control Module |
|---|---|
|
Use Scenario: Isolating analog sensor outputs (e.g., thermistor, potentiometer) from noisy MCU ADC input lines while maintaining low-power sleep mode. IC Role / Device Role / Timing Role: Dual buffer provides noise-immune signal conditioning and enables/disables sensor channel access via OE control. Use Value: Schmitt-trigger inputs reject EMI-induced glitches; IOFF prevents sensor bias leakage during MCU deep-sleep, preserving measurement accuracy. |
Use Scenario: Driving LIN bus transceiver enable lines and LED status indicators from a 3.3 V microcontroller in door module ECUs. IC Role / Device Role / Timing Role: 3-state outputs allow shared control line routing; low propagation delay ensures precise timing alignment with LIN protocol frames. Use Value: 1.4 ns tpd meets LIN timing jitter budgets; −40 °C to +125 °C rating guarantees reliability in under-dash environments. |
| Portable Medical Wearable | Smart Home Hub Baseband |
|
Use Scenario: Level-shifting and buffering between a 1.2 V Bluetooth SoC and 3.3 V environmental sensor array in a patch-style monitor. IC Role / Device Role / Timing Role: Acts as bidirectional voltage translator using overvoltage-tolerant inputs and rail-swing outputs. Use Value: 0.8 V minimum VCC enables operation directly from single-cell Li-ion (2.8–4.2 V) via LDO; ICC ≤1.4 μA extends 7-day battery runtime. |
Use Scenario: Enabling/disabling multiple Zigbee and Thread radio modules on a shared SPI bus in a home automation gateway. IC Role / Device Role / Timing Role: Dual 3-state buffers isolate radio chip selects, preventing bus contention during firmware updates. Use Value: Independent OE control per channel allows staggered activation; low capacitive load (CI = 0.9 pF) minimizes SPI signal distortion at 10 MHz. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G126DBVR | Wider VCC range (1.65–5.5 V); higher ICC (10 μA typ); no IOFF; no Schmitt inputs. | Requires external pull-ups for open-drain compatibility; unsuitable for partial power-down systems. | Select when interfacing legacy 5 V peripherals or where higher drive strength (24 mA) is needed over ultra-low power. |
| 74LVC2G126GM,132 | Same XSON8 package (SOT833-1); identical pinout; lacks IOFF and Schmitt inputs; max temp +85 °C only. | Not qualified for automotive or extended industrial temperature use; higher noise susceptibility on slow edges. | Choose for cost-sensitive consumer applications where −40 °C to +125 °C and IOFF are not required. |
Compared with SN74LVC2G126DBVR and 74LVC2G126GM,132, the 74AUP2G126GN,115 uniquely combines sub-μA ICC, IOFF, Schmitt inputs, and full automotive temperature range - making it the only option for battery-critical, hot-swap-safe, noise-prone embedded control paths.
Availability
74AUP2G126GN,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body electronics, portable medical wearables, and smart home hub baseband designs requiring stable component supply across long production lifecycles.
Supply support for 74AUP2G126GN,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert specializing in high-performance, energy-efficient logic, discrete, and MOSFET solutions, with manufacturing rooted in process innovation and automotive-grade quality systems.
The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and thermally constrained applications, delivering CMOS logic performance with near-zero static power consumption and robust mixed-voltage interoperability.
FAQ
Can 74AUP2G126GN,115 operate with VCC = 0.8 V while driving a 3.3 V input signal?
Yes. Its inputs are overvoltage tolerant up to 3.6 V independent of VCC, so a 3.3 V signal applied to 1A or 2A is safe at VCC = 0.8 V. Output swing remains limited to 0.8 V, but input recognition is guaranteed per VIH/VIL specs down to 0.8 V.
What is the maximum capacitive load the outputs can drive while maintaining 1.4 ns propagation delay?
The 1.4 ns tpd is specified at CL = 5 pF and VCC = 3.3 V. At CL = 15 pF, tpd increases to 2.0 ns (Tamb = 25 °C); at CL = 30 pF, it rises to 2.7 ns. For <2 ns delay, keep total load ≤10 pF including trace and probe capacitance.
How does the IOFF feature behave when VCC is ramping from 0 V to nominal?
IOFF activates when VCC falls below ~0.2 V and remains active until VCC exceeds ~0.5 V. During this transition, output leakage stays ≤±0.75 μA, preventing current injection into downstream circuits even during brown-out conditions.
Is the XSON8 (SOT1116) package of 74AUP2G126GN,115 compatible with reflow profiles for lead-free assembly?
Yes. SOT1116 is qualified for IPC/JEDEC J-STD-020D moisture sensitivity level 1 and supports peak reflow temperatures up to 260 °C. Recommended profile follows SnAgCu (SAC305) with ramp rate ≤3 °C/s and time above 217 °C ≤60 s.
74AUP2G126GN,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 8-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XSON (1.35x1)
74AUP2G126GN,115 FAQ
1.How can I place an order for 74AUP2G126GN,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G126GN,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G126GN,115 reliable?
The price and inventory of 74AUP2G126GN,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G126GN,115 is usually 5 days.
3.What payment methods are accepted for 74AUP2G126GN,115?
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4.How is shipping managed for 74AUP2G126GN,115?
74AUP2G126GN,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP2G126GN,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G126GN,115?
For technical support, including 74AUP2G126GN,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G126GN,115 requirements.
6.How does Aetrix verify that 74AUP2G126GN,115 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G126GN,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G126GN,115 meets industry standards.
7.What is the process for return or replacement of 74AUP2G126GN,115?
All 74AUP2G126GN,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G126GN,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G126GN,115 part is unused and in its original packaging.
Return procedure for 74AUP2G126GN,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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