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Nexperia USA Inc. 74AUP2G126GS,115
- Part No.:
- 74AUP2G126GS,115
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 8-XFDFN
- Datasheet:
-
74AUP2G126GS,115.pdf
- Description:
- 74AUP2G126 - LOW-POWER DUAL BUFF
- Quantity:
- Payment:
- Shipping:
Inventory:132,138
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Product details
Overview
74AUP2G126GS,115 from Nexperia is a dual 3-state buffer/line driver with Schmitt-trigger inputs, operating across 0.8 V to 3.6 V supply, delivering ICC ≤ 1.4 μA (max at −40 °C to +125 °C), tpd ≤ 4.4 ns (VCC = 3.3 V, CL = 5 pF), and IOFF-enabled partial power-down protection. It serves in low-power I/O expansion and bus isolation in portable sensor nodes and battery-powered microcontroller interfaces.
For engineers reviewing the 74AUP2G126GS,115 datasheet, 74AUP2G126GS,115 pinout, 74AUP2G126GS,115 application, or 74AUP2G126GS,115 equivalent, key selection criteria include ultra-low static current, guaranteed 3-state output disable under VCC = 0 V, Schmitt-trigger noise immunity for slow-rising control signals, and XSON8 package compatibility with high-density PCB layouts.
Technical Context
This device implements two independent non-inverting buffers, each with active-HIGH output enable (1OE, 2OE) and Schmitt-trigger input thresholds (VIH/VIL varying with VCC). The IOFF circuit actively disables outputs and blocks backflow current when VCC = 0 V, enabling safe hot-insertion and multi-rail system partitioning.
Dynamic performance is characterized by propagation delay (tpd), enable time (ten), and disable time (tdis), all specified across VCC = 0.8 V–3.6 V and temperature (−40 °C to +125 °C), with load-dependent timing (CL = 5–30 pF) and defined measurement points per JEDEC JESD65B-compliant test circuits.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - supports single-supply operation across 1.0 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Max ICC (−40 °C to +125 °C) | 1.4 μA - enables >10-year battery life in always-on sensor interface applications with infrequent wake-up cycles. |
| tpd (VCC = 3.3 V, CL = 5 pF) | 4.4 ns - ensures timing closure in 100+ MHz digital control loops with minimal added latency. |
| IOFF Leakage (VCC = 0 V) | ±0.75 μA - prevents destructive backfeed current during partial power-down of host MCU or peripheral subsystems. |
| Input Threshold Hysteresis | Typical 100 mV - rejects noise on slow-rising enable or data lines in noisy industrial environments. |
| ESD Robustness | HBM >5000 V, CDM >1000 V - withstands handling and board-level ESD events without external protection. |
| Operating Temperature | −40 °C to +125 °C - qualified for under-hood automotive, industrial motor drives, and outdoor IoT edge nodes. |
Pinout & Package
XSON8 package (SOT1203): extremely thin no-lead outline, 1.35 mm × 1.0 mm × 0.35 mm body, 0.5 mm pitch, wettable flank terminals for automated optical inspection (AOI).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1OE | Active-HIGH output enable for Channel 1 - drives 1Y to high-impedance when LOW; tied to MCU GPIO for dynamic bus arbitration. |
| 2 | 1A | Data input for Channel 1 - Schmitt-triggered to tolerate rise/fall times up to 200 ns/V, eliminating need for external RC filtering. |
| 3 | 2Y | Data output for Channel 2 - 3-state capable, compatible with shared bus topologies requiring contention-free driving. |
| 4 | GND | Digital ground reference - must be connected to system ground plane with low-inductance path to minimize switching noise coupling. |
| 5 | 2A | Data input for Channel 2 - electrically identical to 1A; supports dual independent signal paths or mirrored buffering. |
| 6 | 1Y | Data output for Channel 1 - matches 2Y drive strength (±4 mA @ VCC = 3.0 V) and timing behavior. |
| 7 | 2OE | Active-HIGH output enable for Channel 2 - enables independent gating of each channel's output, supporting selective bus loading. |
| 8 | VCC | Power supply input - requires local 100 nF ceramic decoupling placed within 2 mm of pin to suppress high-frequency supply ripple. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low static power | ICC ≤ 1.4 μA over full temperature range - reduces system standby power budget by >95% vs. standard AHC/AHCT logic. |
| IOFF partial power-down | Blocks backflow current when VCC = 0 V - eliminates need for external isolation switches in multi-voltage domain systems. |
| Schmitt-trigger inputs | Hysteresis ≥100 mV - accepts slow, noisy control signals (e.g., mechanical switch debouncing, long trace routing) without metastability. |
| Overvoltage-tolerant inputs | Accepts up to 3.6 V regardless of VCC - allows interfacing with higher-voltage peripherals while powered from 1.2 V or 1.8 V rails. |
| JEDEC-compliant packaging | SOT1203 (XSON8) with wettable flanks - supports automated optical inspection and high-yield reflow soldering in volume SMT production. |
Applications
| Industrial Sensor Interface | Portable Medical Device I/O |
|---|---|
|
Use Scenario: Isolating analog sensor outputs (e.g., thermistor, pressure transducer) from a low-power MCU ADC input during sleep mode. IC Role / Device Role / Timing Role: Dual buffer provides noise-immune signal conditioning and controlled 3-state disconnect to prevent sensor loading during MCU deep-sleep. Use Value: Enables <1 μA system sleep current by eliminating leakage paths through unpowered peripherals while maintaining fast wake-up response (<5 ns enable time). |
Use Scenario: Expanding GPIO count on a wearable ECG monitor SoC to drive LED indicators and button inputs without increasing BOM cost or board area. IC Role / Device Role / Timing Role: Acts as bidirectional I/O expander buffer with independent enable control per channel for flexible peripheral management. Use Value: Reduces total solution size by 30% vs. discrete MOSFET-based isolation, with guaranteed 3.3 V-compatible outputs even when MCU runs at 1.2 V. |
| Automotive Body Control Module | Smart Home Hub Signal Routing |
|
Use Scenario: Level-shifting and isolating LIN bus diagnostic signals between 5 V legacy modules and 3.3 V microcontroller subsystems. IC Role / Device Role / Timing Role: Buffer with overvoltage-tolerant inputs accepts 5 V LIN pulses while powered from 3.3 V rail; IOFF protects MCU during ignition-off state. Use Value: Eliminates need for external voltage translators and reverse-current blocking diodes, reducing component count by 4 parts per channel. |
Use Scenario: Managing shared I²C/SPI bus access among multiple wireless SoCs (Zigbee, Thread, BLE) in a home automation gateway. IC Role / Device Role / Timing Role: Provides 3-state bus isolation between competing masters, with Schmitt-triggered OE inputs immune to crosstalk-induced glitches. Use Value: Prevents bus contention faults and lockups during simultaneous master arbitration, improving system uptime by >99.99% in field deployments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC2G126GW,125 | Higher ICC (max 4 μA), wider VCC range (1.65 V–5.5 V), no IOFF circuitry | Lacks power-down isolation; unsuitable for partial-power-down systems where VCC may collapse independently | Select only if interfacing with 5 V peripherals and full-system power cycling is guaranteed |
| SN74AUP2G126DCKR | Identical electrical specs but VSSOP8 (SOT765-1) package; 2.3 mm body width vs. 1.35 mm | Requires 2.5× more PCB area; not suitable for space-constrained wearables or miniaturized modules | Choose only when hand-soldering or legacy footprint compatibility is required |
Compared with 74LVC2G126GW,125 and SN74AUP2G126DCKR, the 74AUP2G126GS,115 uniquely combines sub-μA static current, IOFF-enabled backflow prevention, and 1.35 mm × 1.0 mm XSON8 packaging-making it the sole option for ultra-low-power, high-density, multi-rail-isolated designs.
Availability
74AUP2G126GS,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical devices, automotive body control modules, and smart home hub signal routing requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for 74AUP2G126GS,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert specializing in high-performance, energy-efficient logic, analog, and discrete components, with leadership in automotive-grade reliability and scalable manufacturing.
The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and thermally constrained applications demanding nanowatt static power, robust noise immunity, and seamless voltage-domain interoperability.
FAQ
Can 74AUP2G126GS,115 operate reliably at 0.8 V supply?
Yes. The device is fully characterized down to 0.8 V, with guaranteed tpd ≤ 20.6 ns (CL = 5 pF), VIH ≥ 0.70 × VCC, and ICC ≤ 0.5 μA at 25 °C. All DC and AC parameters meet specification across the full 0.8 V–3.6 V range, enabling direct integration into energy-harvesting and sub-1 V MCU systems.
Does the IOFF feature require external biasing or configuration?
No. IOFF activates automatically when VCC = 0 V, regardless of input/output voltage levels. No external resistors, configuration registers, or enable sequencing is needed-the circuit internally disables outputs and blocks current flow above ±0.75 μA, meeting JESD78 Class II latch-up immunity requirements.
What is the maximum capacitive load this buffer can drive while maintaining timing specs?
The datasheet specifies timing up to CL = 30 pF. At VCC = 3.3 V, tpd remains ≤ 8.3 ns and tdis ≤ 12.0 ns under 30 pF load. Driving >30 pF will increase propagation and disable delays nonlinearly; for loads >50 pF, consider adding series termination or using a higher-drive buffer variant.
How does the Schmitt-trigger input improve system robustness?
Schmitt-trigger inputs provide ≥100 mV hysteresis, rejecting noise spikes and slow edge rates (up to 200 ns/V) that would cause chatter or metastability in standard CMOS inputs. This eliminates external RC filters in applications like pushbutton interfaces, relay feedback monitoring, and long-cable sensor links.
74AUP2G126GS,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 8-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XSON (1.35x1)
74AUP2G126GS,115 FAQ
1.How can I place an order for 74AUP2G126GS,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G126GS,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G126GS,115 reliable?
The price and inventory of 74AUP2G126GS,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G126GS,115 is usually 5 days.
3.What payment methods are accepted for 74AUP2G126GS,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP2G126GS,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP2G126GS,115?
74AUP2G126GS,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP2G126GS,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G126GS,115?
For technical support, including 74AUP2G126GS,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G126GS,115 requirements.
6.How does Aetrix verify that 74AUP2G126GS,115 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G126GS,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G126GS,115 meets industry standards.
7.What is the process for return or replacement of 74AUP2G126GS,115?
All 74AUP2G126GS,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G126GS,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G126GS,115 part is unused and in its original packaging.
Return procedure for 74AUP2G126GS,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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