Nexperia USA Inc. 74AUP2G126GXX

Overview

74AUP2G126GXX from Nexperia is a dual CMOS buffer/line driver with independent 3-state outputs controlled by active-HIGH output enable inputs (1OE, 2OE). It operates across 0.8 V to 3.6 V supply, delivers <0.9 μA max ICC at 25 °C, features Schmitt-trigger inputs for noise immunity, and supports partial power-down via IOFF circuitry. It is used in low-power I/O expansion and bus isolation in portable sensor nodes and battery-powered microcontroller peripherals.

For engineers reviewing the 74AUP2G126GXX datasheet, 74AUP2G126GXX pinout, 74AUP2G126GXX application, or 74AUP2G126GXX equivalent, key selection criteria include ultra-low static current, wide VCC compatibility, guaranteed 3-state behavior during power sequencing, and thermal-enhanced X2SON8 packaging options for space-constrained PCBs.

Technical Context

The device implements two independent non-inverting buffers, each with dedicated output enable control. Its Schmitt-trigger inputs tolerate slow-rising signals and reject high-frequency noise, enabling robust operation in noisy industrial or automotive environments. The IOFF circuit actively disables outputs when VCC = 0 V, preventing backflow current into powered-down subsystems.

All logic thresholds scale with VCC (e.g., VIH = 0.65×VCC min at 0.9–1.95 V), ensuring consistent switching behavior across voltage domains. Propagation delay is load- and voltage-dependent - as low as 1.4 ns (CL = 5 pF, VCC = 3.3 V) for data path (nA→nY) and 1.3 ns for enable path (nOE→nY), supporting timing-critical interface bridging.

Key Specifications

Pinout & Package

X2SON8 package (SOT1233-2): plastic thermal-enhanced extremely thin small outline, 8-terminal, no leads, body size 1.35 × 0.8 × 0.32 mm, exposed thermal pad on bottom.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual buffer/line driver applications.

Compared with SN74LVC2G126DBVR and 74AUP2G04GW,8, the 74AUP2G126GXX uniquely combines ultra-low ICC, full IOFF protection, and independent 3-state control - making it the sole option for battery-powered, multi-voltage, and hot-pluggable designs requiring zero standby leakage and dynamic bus arbitration.

Availability

74AUP2G126GXX is available at Aetrix Electronics and suitable for industrial sensor interfaces, low-power MCU I/O expansion, automotive body control modules, and IoT edge node bus isolation requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP2G126GXX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable components for automotive, industrial, and consumer markets, with leadership in logic, MOSFETs, and ESD protection.

The 74AUP (Advanced Ultra-low Power) product line targets energy-sensitive applications such as wearables, battery-powered sensors, and always-on IoT endpoints, emphasizing sub-μA static current and wide-VCC interoperability.

FAQ

What is the maximum capacitive load the 74AUP2G126GXX can drive while maintaining specified propagation delay?

The datasheet specifies tpd performance up to CL = 30 pF across all VCC ranges. At VCC = 3.3 V and CL = 30 pF, tpd is 2.7 ns (min) to 5.8 ns (max). Driving loads beyond 30 pF increases delay nonlinearly and may violate setup/hold timing in synchronous interfaces - external series termination or buffer staging is recommended above this limit.

Does the 74AUP2G126GXX support mixed-voltage operation where inputs exceed VCC?

Yes - inputs are overvoltage tolerant up to 3.6 V regardless of VCC setting (e.g., VCC = 1.8 V with VI = 3.3 V is valid). This enables safe interfacing with higher-voltage peripherals without external clamping diodes, provided input current remains within ±0.1 μA leakage limits.

How does the IOFF feature behave when VCC is ramping from 0 V to nominal voltage?

IOFF activates automatically when VCC drops below ~0.2 V and remains active until VCC rises above ~0.4 V. During this transition, outputs stay in high-impedance state with leakage ≤±0.75 μA, preventing current backflow from any externally driven signal line into the unpowered IC.

Can both output enable inputs (1OE and 2OE) be tied together for single-control operation?

Yes - tying 1OE and 2OE simplifies control logic and maintains functional equivalence to a single dual-channel buffer. No timing skew or contention occurs, as both enables share identical electrical characteristics and propagation delay (1.3 ns typ from nOE to nY).