Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Gates and Inverters

Nexperia USA Inc. 74AUP2G132DC,125

Name: 74AUP2G132DC,125
Brand: Nexperia USA Inc.
SKU: 74AUP2G132DC,125
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 74AUP2G132DC,125

Manufacturer:: Nexperia USA Inc.

Category:: Gates and Inverters

Package:: 8-VFSOP (0.091", 2.30mm Width)

Datasheet:: 74AUP2G132DC,125.pdf

Description:: IC GATE NAND 2CH 2-INP 8VSSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,150

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

74AUP2G132DC from Nexperia is a dual 2-input NAND gate with Schmitt-trigger inputs, designed for noise-immune signal conditioning in low-voltage digital systems. It operates across 0.8 V to 3.6 V, delivers ICC ≤ 1.4 μA (max) at −40 °C to +125 °C, features IOFF circuitry for partial power-down protection, and supports wave shaping in battery-powered sensor interfaces.

For engineers reviewing the 74AUP2G132DC datasheet, 74AUP2G132DC pinout, 74AUP2G132DC application, or 74AUP2G132DC equivalent, key selection criteria include Schmitt-trigger hysteresis (VH = 0.79–1.31 V at VCC = 3.0 V), ultra-low static current, IOFF-enabled bus isolation, and VSSOP8 package compatibility with high-density PCB layouts.

Technical Context

The device integrates two independent NAND gates, each with asymmetric Schmitt-trigger input thresholds (VT+ = 1.88–2.32 V, VT− = 0.88–1.24 V at VCC = 3.0 V), enabling robust noise rejection on slow-rising signals. Its IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current up to ±0.75 μA.

Dynamic performance is load- and voltage-dependent: propagation delay ranges from 1.4 ns (VCC = 3.0 V, CL = 5 pF) to 10.1 ns (VCC = 3.0 V, CL = 30 pF), while CPD remains stable at 4.4 pF across 3.0–3.6 V, supporting predictable dynamic power estimation.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage Range	0.8 V to 3.6 V - enables direct interfacing with I/Os of modern ultra-low-power MCUs (e.g., ARM Cortex-M0+, MSP430) without level shifters
Max ICC (−40 °C to +125 °C)	1.4 μA - ensures <1 μW static power at 1.8 V, critical for multi-year battery operation in IoT endpoints
Hysteresis Voltage (VH)	0.79–1.31 V at VCC = 3.0 V - provides ≥440 mV noise margin for reliable edge detection on noisy sensor or switch inputs
IOFF Leakage (VCC = 0 V)	±0.75 μA - prevents cross-talk and backfeed in hot-swappable or power-gated subsystems
Propagation Delay (tpd)	1.4–10.1 ns - scales predictably with load capacitance (5–30 pF) and supply (0.8–3.6 V), supporting timing-critical debounce
ESD Robustness	HBM >5000 V, CDM >1000 V - eliminates need for external ESD protection in industrial control panels and handheld devices
Operating Temperature	−40 °C to +125 °C - qualified for under-hood automotive modules and industrial motor drives

Pinout & Package

VSSOP8 (SOT765-1) package: plastic very thin shrink small outline, 8 leads, 2.3 mm body width, 0.5 mm pitch, exposed pad not present.

Pin/Terminal	Circuit Role	Design Meaning
1A, 5	Input A of Gate 1 / Input A of Gate 2	Dual independent logic inputs accepting 0–3.6 V; Schmitt-triggered for noise immunity
2, 6	Input B of Gate 1 / Input B of Gate 2	Second input per gate; threshold hysteresis enables clean switching on slow analog-like signals
7, 3	Output Y of Gate 1 / Output Y of Gate 2	Push-pull CMOS outputs driving loads up to ±4 mA at 3.0 V; rail-to-rail VOH/VOL
4	GND	Reference ground for all inputs, outputs, and internal circuitry; must be low-impedance for noise suppression
8	VCC	Primary supply rail; IOFF activation occurs automatically when VCC = 0 V

Key Features

Feature	Design Value
Wide VCC range (0.8–3.6 V)	Eliminates level translation between 1.2 V, 1.8 V, 2.5 V, and 3.3 V domains in mixed-supply SoC peripherals
IOFF partial power-down	Enables live insertion into powered backplanes by disabling outputs and blocking damaging backflow current
High noise immunity	Minimum 440 mV hysteresis at 3.0 V suppresses EMI-induced glitches on long traces or unshielded cables
Low dynamic power	CPD = 4.4 pF allows sub-μW dynamic dissipation at 1 MHz, extending battery life in always-on wake-up circuits
JEDEC-compliant voltage standards	Meets JESD8-12 through JESD8C - certified interoperable with industry-standard low-voltage logic families

Applications

Wave Shaping

Astable Multivibrator

Use Scenario: Converting irregular analog sensor output (e.g., thermistor voltage drift) into clean digital pulses for microcontroller ADC triggering.

IC Role / Device Role / Timing Role: Dual NAND gate configured as a Schmitt-trigger inverter with RC feedback to square up slow edges and reject noise.

Use Value: Eliminates external op-amp comparators and reduces BOM count by 2–3 components per channel in environmental monitoring nodes.

Use Scenario: Generating precise clock signals for LED flash timing or status indicator blinking in portable medical devices.

IC Role / Device Role / Timing Role: Cross-coupled NAND gates forming a free-running oscillator; frequency set by external R/C network.

Use Value: Achieves <±5% frequency stability over −40 °C to +85 °C without crystal, reducing cost and board space vs. dedicated timer ICs.

Monostable Multivibrator

Industrial Switch Debounce

Use Scenario: Producing fixed-duration pulses for PLC input synchronization or solenoid actuation timing.

IC Role / Device Role / Timing Role: Single-shot circuit using one NAND gate and RC network to generate programmable pulse widths (1 ms–1 s).

Use Value: Provides deterministic, temperature-stable pulse generation without software overhead or MCU timer resource consumption.

Use Scenario: Cleaning mechanical contact bounce from emergency stop buttons or limit switches in factory automation panels.

IC Role / Device Role / Timing Role: Schmitt-trigger inputs filter chatter; NAND logic ensures clean, glitch-free digital transitions to safety controllers.

Use Value: Meets IEC 61508 SIL-2 requirements for hardware fault tolerance in safety-critical input conditioning.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual Schmitt-trigger NAND gate applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC2G132DCUR	Wider VCC range (1.65–5.5 V); higher ICC (max 10 μA); no IOFF	Supports legacy 5 V systems but lacks power-down isolation for hot-swap use cases	Select when interfacing with 5 V logic or when IOFF is unnecessary
74LVC2G132GM125	Same VCC (1.65–5.5 V); XQFN8 package (1.4 × 1.0 × 0.4 mm); no IOFF; lower hysteresis (VH ≈ 0.5 V at 3.3 V)	Better thermal performance in space-constrained designs, but reduced noise margin vs. AUP series	Select for ultra-thin wearables where footprint and height are prioritized over noise immunity

Compared with SN74LVC2G132DCUR and 74LVC2G132GM125, the 74AUP2G132DC offers superior low-voltage operation (down to 0.8 V), lowest ICC (<1.4 μA), and IOFF-making it optimal for energy harvesting, battery longevity, and partial-power-down architectures where leakage and voltage scalability are critical.

Availability

74AUP2G132DC is available at Aetrix Electronics and suitable for wave shapers, monostable multivibrators, industrial switch debouncers, and battery-powered sensor interfaces requiring stable component supply across automotive, industrial, and medical end markets.

Supply support for 74AUP2G132DC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable logic, discrete, and MOSFET solutions with leadership in efficiency and miniaturization.

The 74AUP (Advanced Ultra-low Power) logic family targets ultra-low-power digital signal conditioning in space- and energy-constrained applications, emphasizing sub-1-μA static current and wide-VCC interoperability.

FAQ

What is the minimum operating voltage for reliable Schmitt-trigger operation?

The 74AUP2G132DC maintains defined Schmitt thresholds down to VCC = 0.8 V, with VT+ = 0.30 V and VT− = 0.10 V (typical) at that rail. Hysteresis remains functional across the full 0.8–3.6 V range, enabling consistent noise rejection even in energy-harvesting systems with fluctuating supply.

Does the IOFF feature require external control signals?

No. IOFF activates automatically when VCC drops to 0 V-no enable pin or external logic is needed. The output enters high-impedance state, limiting backflow current to ±0.75 μA, making it ideal for passive power gating in modular systems.

Can this device drive standard 50 Ω transmission lines?

No. With ±4 mA output drive at 3.0 V, the 74AUP2G132DC is rated for capacitive loads up to 50 pF-not 50 Ω resistive termination. For transmission line driving, use a dedicated buffer or line driver IC with appropriate slew rate and drive strength.

How does propagation delay vary with supply voltage and load?

tpd decreases as VCC increases and CL decreases: at VCC = 3.0 V, tpd = 1.4 ns (CL = 5 pF) rising to 10.1 ns (CL = 30 pF); at VCC = 0.8 V, tpd exceeds 22 ns even at CL = 5 pF. Designers must characterize delay under actual operating VCC and load conditions.

74AUP2G132DC,125 Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: 74AUP

Package/Case:: 8-VFSOP (0.091", 2.30mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Logic Type:: NAND Gate

Number of Circuits:: 2

Number of Inputs:: 2

Features:: Schmitt Trigger

Voltage - Supply:: 0.8V ~ 3.6V

Current - Quiescent (Max):: 500 nA

Current - Output High, Low:: 4mA, 4mA

Input Logic Level - Low:: 0.1V ~ 0.88V

Input Logic Level - High:: 0.6V ~ 2.29V

Max Propagation Delay @ V, Max CL:: 7.8ns @ 3.3V, 30pF

Operating Temperature:: -40°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-VSSOP

74AUP2G132DC,125 FAQ

1.How can I place an order for 74AUP2G132DC,125 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP2G132DC,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AUP2G132DC,125 reliable?

The price and inventory of 74AUP2G132DC,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G132DC,125 is usually 5 days.

3.What payment methods are accepted for 74AUP2G132DC,125?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP2G132DC,125 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74AUP2G132DC,125?

74AUP2G132DC,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74AUP2G132DC,125 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74AUP2G132DC,125?

For technical support, including 74AUP2G132DC,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G132DC,125 requirements.

6.How does Aetrix verify that 74AUP2G132DC,125 is sourced from the original manufacturer or authorized distributors?

All 74AUP2G132DC,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G132DC,125 meets industry standards.

7.What is the process for return or replacement of 74AUP2G132DC,125?

All 74AUP2G132DC,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G132DC,125, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP2G132DC,125 part is unused and in its original packaging.

Return procedure for 74AUP2G132DC,125:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

2026-08-11 LDO Regulator: Dropout Voltage, Noise, PSRR and Power Dissipation

LDO regulator guide covering low dropout voltage, power dissipation, thermal design, PSRR, output noise, capacitor stability, adjustable LDO circuits, LDO vs buck converter and datasheet selection chec…

2026-08-06 Conditional Access Module: CAM, CI/CI+ and DVB Security

Conditional Access Module guide covering CAM meaning, CI/CI+ interface, smart card authorization, DVB security workflow, TV and set-top box compatibility, internal electronics, ESD protection, connecto…

2026-08-03 Electronic Component Obsolescence: EOL Risks, Replacement Options and Last-Time Buy Strategy

Guide to electronic component obsolescence covering EOL risk, PCN/PDN notices, last-time buy planning, replacement options, form-fit-function validation, counterfeit risk and BOM lifecycle management.

2026-07-29 18650 Battery: Voltage, Capacity, Charging and Pack Design

18650 battery guide covering lithium-ion cell basics, 3.6V/3.7V voltage, 4.2V charging, mAh and Wh capacity, protected cells, chargers, BMS, series-parallel packs, holders, welding and sourcing checks.…

2026-07-27 Hall Effect Sensor: Working Principle, Types, Circuits and Applications

Hall effect sensor guide covering working principle, linear and digital sensors, Arduino circuits, current sensing, speed detection, automotive applications, A3144 examples, signal filtering and datash…

2026-07-20 Product Change Notification (PCN) in Electronic Components: Meaning and Supply Chain Response

Product Change Notification guide for electronic components, covering PCN meaning, PCN vs PDN/EOL, common change types, risk levels, form-fit-function review, engineering validation, BOM control, LTB/L…

2026-07-19 Blend Door Actuator: Symptoms, Location, Reset and Replacement Guide

A practical guide to blend door actuators, covering HVAC function, symptoms, location, AC and heater issues, reset and calibration, replacement cost, electrical diagnosis, compatibility checks, and rep…

2026-07-17 Raspberry Pi Alternatives: Chip-Level Comparison, Compatibility and Replacement Guide

Engineering guide to Raspberry Pi alternatives, covering chip-level differences, Orange Pi, ROCK, Jetson, Banana Pi, NanoPi, Compute Module, Pico, GPIO, camera, HAT compatibility, and replacement risks…