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NXP Semiconductors 74AUP2G132GD,125
- Part No.:
- 74AUP2G132GD,125
- Manufacturer:
- NXP Semiconductors
- Category:
- Gates and Inverters
- Package:
- 8-XFDFN
- Datasheet:
-
74AUP2G132GD,125.pdf
- Description:
- IC GATE NAND 2CH 2-INP 8-XSON
- Quantity:
- Payment:
- Shipping:
Inventory:447,102
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Product details
Overview
74AUP2G132GD,125 from Nexperia is a dual 2-input NAND gate with Schmitt-trigger inputs, designed for noise-immune signal conditioning in low-voltage digital systems. It operates across 0.8 V to 3.6 V, delivers ICC ≤ 0.9 μA (max) at +125 °C, features IOFF for partial power-down protection, and supports −40 °C to +125 °C ambient operation - used in wave shaping and multivibrator circuits.
For engineers reviewing the 74AUP2G132GD,125 datasheet, 74AUP2G132GD,125 pinout, 74AUP2G132GD,125 application, or 74AUP2G132GD,125 equivalent, this page provides verified package mapping (XSON8, SOT1116), confirmed Schmitt-trigger hysteresis (VH = 0.79–1.31 V at VCC = 3.0 V), IOFF leakage (±0.75 μA), propagation delay (1.4–6.2 ns at CL = 5 pF), and functional substitution guidance.
Technical Context
This device implements two independent NAND logic gates, each with Schmitt-trigger input thresholds (VT+ = 1.88–2.32 V, VT− = 0.88–1.24 V at VCC = 3.0 V) enabling robust noise rejection on slow-rising signals. Its IOFF circuit actively disables outputs during VCC = 0 V, preventing backflow current in mixed-supply or hot-swap systems.
It complies with JEDEC standards JESD8-12 through JESD8C across five voltage bands and meets HBM ESD > 5000 V and CDM > 1000 V. Input overvoltage tolerance up to 3.6 V allows interfacing with higher-voltage logic without level shifters.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - enables direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains |
| Max ICC (Tamb = −40 °C to +125 °C) | 1.4 μA - ensures ultra-low static power in battery-powered or always-on sensor nodes |
| IOFF Leakage (VCC = 0 V) | ±0.75 μA - prevents damaging back-current during partial power-down sequences |
| Propagation Delay (VCC = 3.0 V, CL = 5 pF) | 1.4–6.2 ns - supports timing-critical edge detection and pulse generation up to ~100 MHz |
| Hysteresis Voltage (VCC = 3.0 V) | 0.79–1.31 V - rejects noise spikes up to 1.3 V peak-to-peak without false triggering |
| Input Overvoltage Tolerance | 3.6 V - permits safe connection to 3.3 V I/O even when VCC = 0.8 V |
| ESD Rating (HBM) | > 5000 V - exceeds JEDEC JS-001 Class 3A for handling robustness in assembly |
Pinout & Package
XSON8 package (SOT1116): plastic extremely thin small outline, no leads, 8 terminals, body size 1.2 mm × 1.0 mm × 0.35 mm, thermal pad omitted.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1A, 2A | Data input (Gate 1 and Gate 2) | Schmitt-triggered NAND inputs - accept slow edges and reject noise via hysteresis |
| 1B, 2B | Data input (Gate 1 and Gate 2) | Second input per gate; all four inputs tolerate 3.6 V regardless of VCC |
| 1Y, 2Y | Data output (Gate 1 and Gate 2) | CMOS push-pull outputs; IOFF disables both when VCC = 0 V |
| VCC | Supply voltage | Single rail powers both gates; IOFF activation requires VCC = 0 V |
| GND | Ground reference | Common return for inputs, outputs, and internal biasing networks |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range | 0.8 V to 3.6 V enables drop-in use across multiple supply domains without redesign |
| IOFF circuitry | Active output disable at VCC = 0 V prevents backfeed in multi-rail power sequencing |
| High noise immunity | Typical hysteresis 1.1 V at 3.0 V VCC suppresses EMI-induced glitches on long traces |
| Low dynamic power | CPD = 3.2 pF (VCC = 1.65–1.95 V) minimizes switching loss in high-frequency clock shaping |
| JEDEC-compliant operation | Validated across five voltage bands (JESD8-12 to JESD8C) for global system compatibility |
Applications
| Wave Shaping | Astable Multivibrator |
|---|---|
Use Scenario: Converting noisy or slow-rising analog sensor outputs (e.g., thermistor-based comparators) into clean digital pulses for microcontroller capture. IC Role / Device Role / Timing Role: Dual Schmitt NAND acts as edge cleaner and level translator between sub-1 V analog front-end and 1.8 V MCU I/O. Use Value: Eliminates need for external RC filters or dedicated comparator ICs, reducing BOM count by one active component. | Use Scenario: Generating precise square-wave clocks for LED flash timing or sensor sampling in portable medical devices. IC Role / Device Role / Timing Role: Cross-coupled NAND gates form self-oscillating relaxation oscillator with frequency set by external RC network. Use Value: Achieves stable oscillation down to 0.8 V supply, enabling operation from single-cell Li-ion (2.5–4.2 V) via LDO dropout margin. |
| Monostable Multivibrator | Power Sequencing Monitor |
Use Scenario: Creating fixed-duration enable pulses for peripheral wake-up (e.g., BLE radio activation after button press). IC Role / Device Role / Timing Role: One gate configured as monostable trigger; input edge initiates output pulse shaped by RC time constant. Use Value: Pulse width accuracy maintained across −40 °C to +125 °C due to temperature-stable VT+/VT− thresholds. | Use Scenario: Detecting undervoltage lockout (UVLO) faults during multi-rail power-up in industrial PLC modules. IC Role / Device Role / Timing Role: NAND gate compares delayed and raw 3.3 V rail signals; Schmitt input prevents chatter during rail crossing. Use Value: IOFF ensures no current flows from 3.3 V monitoring node into unpowered 1.2 V domain during startup sequencing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual Schmitt NAND gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G132DCUR | Wider VCC range (1.65–5.5 V); higher ICC (10 μA typ); no IOFF | Requires external isolation for partial power-down; unsuitable for sub-1.65 V systems | Select only if 5 V tolerance or legacy LVC logic family compatibility is required |
| 74LVC2G132GM,132 | Same AUP family but XQFN8 (SOT902-2); 0.8–3.6 V; IOFF present; slightly higher ICC (1.8 μA max) | Thermal pad improves power dissipation margin but increases PCB footprint and rework complexity | Prefer for thermally constrained designs where 0.35 mm height is acceptable |
Compared with SN74LVC2G132DCUR and 74LVC2G132GM,132, the 74AUP2G132GD,125 offers lowest ICC (1.4 μA max), smallest footprint (1.2 × 1.0 mm), and guaranteed IOFF - making it optimal for space-constrained, ultra-low-power, and multi-rail sequenced applications.
Availability
74AUP2G132GD,125 is available at Aetrix Electronics and suitable for wave shapers, astable/monostable multivibrators, and power sequencing monitors requiring stable component supply across automotive, industrial, and portable electronics programs.
Supply support for 74AUP2G132GD,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions with leadership in efficiency and miniaturization.
The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and energy-sensitive applications, delivering sub-μA static current and wide-VCC compatibility without sacrificing speed or noise immunity.
FAQ
What is the maximum operating temperature for 74AUP2G132GD,125?
The device is fully specified from −40 °C to +125 °C ambient temperature, with all electrical parameters (including ICC ≤ 1.4 μA, VOH ≥ 2.30 V, VOL ≤ 0.50 V) guaranteed across this full range per Table 6 and Table 7 of the Rev. 11 datasheet.
Does 74AUP2G132GD,125 support partial power-down mode?
Yes - its integrated IOFF circuitry disables both outputs when VCC = 0 V, limiting power-off leakage to ±0.75 μA (max) and preventing destructive back-current flow into powered downstream logic, as validated in Table 7 under ΔIOFF conditions.
Can 74AUP2G132GD,125 interface directly with 3.3 V inputs while running at 1.2 V VCC?
Yes - inputs tolerate up to 3.6 V regardless of VCC level, allowing direct connection to 3.3 V signals without level shifters or clamping diodes, as specified in Table 5 (VI input voltage: −0.5 V to +4.6 V) and Section 2 features.
What package variant does 74AUP2G132GD,125 use?
It uses the XSON8 package per SOT1116 outline: 8-terminal, leadless, 1.2 mm × 1.0 mm × 0.35 mm body, with pin 1 marked in the lower-left corner below the "aE" marking code, as defined in Tables 1 and 2 and Figure 5 of the datasheet.
74AUP2G132GD,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74AUP
- Package/Case:
- 8-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- NAND Gate
- Number of Circuits:
- 2
- Number of Inputs:
- 2
- Features:
- Schmitt Trigger
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Max):
- 500 nA
- Current - Output High, Low:
- 4mA, 4mA
- Input Logic Level - Low:
- 0.1V ~ 0.88V
- Input Logic Level - High:
- 0.6V ~ 2.29V
- Max Propagation Delay @ V, Max CL:
- 7.8ns @ 3.3V, 30pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XSON (2x3)
74AUP2G132GD,125 FAQ
1.How can I place an order for 74AUP2G132GD,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G132GD,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G132GD,125 reliable?
The price and inventory of 74AUP2G132GD,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G132GD,125 is usually 5 days.
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Once your 74AUP2G132GD,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G132GD,125?
For technical support, including 74AUP2G132GD,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G132GD,125 requirements.
6.How does Aetrix verify that 74AUP2G132GD,125 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G132GD,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G132GD,125 meets industry standards.
7.What is the process for return or replacement of 74AUP2G132GD,125?
All 74AUP2G132GD,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G132GD,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G132GD,125 part is unused and in its original packaging.
Return procedure for 74AUP2G132GD,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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