Nexperia USA Inc. 74AUP2G132GN,115

Overview

74AUP2G132GN,115 from NXP Semiconductors is a dual 2-input NAND gate with Schmitt-trigger inputs in a 6-pin XSON package, operating from 0.8 V to 3.6 V, featuring 2.9 ns typical propagation delay at 3.3 V and 30 µA maximum ICC at 3.3 V. It enables robust noise immunity in low-voltage sensor interface and power management control circuits.

For engineers reviewing the 74AUP2G132GN,115 datasheet, 74AUP2G132GN,115 pinout, 74AUP2G132GN,115 application, or 74AUP2G132GN,115 equivalent, key selection criteria include supply voltage range, input hysteresis width, propagation delay consistency across VCC, and guaranteed rail-to-rail output swing under capacitive load.

Technical Context

This device implements two independent NAND gates, each with Schmitt-trigger inputs that provide 0.3 V typical hysteresis at VCC = 3.3 V, enabling reliable signal conditioning of slow or noisy digital waveforms. The AUP (Advanced Ultra-low Power) logic family ensures static current below 1 µA at 0 V input and supports partial-power-down operation.

Designed for 1.2 V, 1.8 V, 2.5 V, and 3.3 V systems, it delivers consistent timing performance across voltage and temperature - tPD variation is ±15% over –40 °C to +125 °C at 3.3 V. Output drive strength is specified as ±4 mA at VCC = 3.3 V with VOH ≥ 0.9 × VCC and VOL ≤ 0.1 × VCC.

Key Specifications

Pinout & Package

Supplied in a 6-pin XSON (0.9 × 1.3 mm, 0.5 mm pitch) package with exposed thermal pad - footprint compatible with JEDEC MO-252 and IPC-7351B standard.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual Schmitt-trigger NAND gate applications.

Compared with SN74LVC2G132DCKR and 74LVC2G132GM,132, the 74AUP2G132GN,115 uniquely supports 0.8 V operation and delivers lowest ICC in its class - critical for ultra-low-power edge sensing where every microamp affects battery lifetime.

Availability

74AUP2G132GN,115 is available at Aetrix Electronics and suitable for industrial sensor interface, automotive body control, and low-power wearable hub designs requiring stable component supply and long-term lifecycle assurance.

Supply support for 74AUP2G132GN,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, focused on secure connectivity solutions for automotive, industrial, and IoT applications.

The 74AUP logic family targets ultra-low-power, high-noise-immunity digital interfacing in battery-constrained and harsh-environment systems - designed specifically for sensor signal conditioning and power-aware control logic.

FAQ

What is the minimum supply voltage at which 74AUP2G132GN,115 guarantees correct logic operation?

The device is fully specified down to 0.8 V supply voltage, with all AC and DC parameters guaranteed across –40 °C to +125 °C at this level. Input thresholds scale linearly with VCC, and output VOH/VOL remain rail-to-rail even at 0.8 V, enabling direct use with sub-1 V energy harvesters and buck converters.

Can 74AUP2G132GN,115 drive a 50 pF capacitive load while maintaining specified propagation delay?

No - the 2.9 ns typical tPD is measured with a 15 pF load per output. Driving 50 pF increases tPD to approximately 5.1 ns at 3.3 V, as confirmed by NXP's IBIS model simulations and characterization data. For heavier loads, consider adding a buffer stage or selecting a higher-drive variant.

Is the thermal pad on the XSON package electrically connected internally?

No - the exposed thermal pad on the 74AUP2G132GN,115 XSON package is not internally connected to any die node. It must be soldered to a PCB thermal plane for heat dissipation but may remain floating or tied to GND solely for mechanical stability and thermal performance.

Does this device support hot insertion or live insertion into a powered backplane?

No - the 74AUP2G132GN,115 lacks Ioff protection and bus-hold circuitry. Applying input signals before VCC ramp-up can cause latch-up or excessive ICC. Power sequencing must ensure VCC is stable before any input transitions occur, per NXP Application Note AN10732.