Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Gates and Inverters

Nexperia USA Inc. 74AUP2G132GS,115

Name: 74AUP2G132GS,115
Brand: Nexperia USA Inc.
SKU: 74AUP2G132GS,115
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 74AUP2G132GS,115

Manufacturer:: Nexperia USA Inc.

Category:: Gates and Inverters

Package:: -

Datasheet:: 74AUP2G132GS,115.pdf

Description:: IC DUAL 2-INP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:89,900

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

74AUP2G132GS,115 from Nexperia is a dual 2-input NAND gate with Schmitt-trigger inputs, designed for noise-immune signal conditioning in low-voltage digital systems. It operates across 0.8 V to 3.6 V, delivers ≤0.9 μA max ICC at −40 °C to +125 °C, features IOFF partial power-down protection, and supports wave shaping in battery-powered sensor interfaces.

For engineers reviewing the 74AUP2G132GS,115 datasheet, 74AUP2G132GS,115 pinout, 74AUP2G132GS,115 application, or 74AUP2G132GS,115 equivalent, key selection criteria include Schmitt-trigger hysteresis (≥0.53 V at VCC = 1.1 V), ultra-low static current, IOFF-enabled bus isolation, and XSON8 package compatibility with high-density PCB layouts.

Technical Context

This device implements two independent NAND logic gates, each with hysteresis-equipped Schmitt-trigger inputs to reject analog noise on slow-rising/falling signals. The IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current during partial power-down-critical for mixed-supply systems.

Input thresholds are voltage-scalable: VT+ ranges from 0.30 V (VCC = 0.8 V) to 2.32 V (VCC = 3.0 V); VT− scales similarly, yielding hysteresis (VH) from 0.07 V to 1.31 V. Propagation delay is load- and voltage-dependent-e.g., 1.4 ns (min) at VCC = 3.0 V, CL = 5 pF-and remains functional down to 0.8 V supply.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage Range	0.8 V to 3.6 V - enables direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters
Max ICC (−40 °C to +125 °C)	1.4 μA - ensures <1 μW static power at 1.8 V, critical for multi-year battery operation
IOFF Leakage (VCC = 0 V)	±0.75 μA - prevents cross-talk and current leakage in powered-down subsystems
VT+ / VT− Hysteresis (VCC = 1.8 V)	≈0.74 V / ≈0.39 V (VH ≈ 0.35 V) - rejects >350 mV of input noise without false triggering
tpd (VCC = 3.0 V, CL = 5 pF)	1.4 ns (min) to 6.2 ns (max) - supports >100 MHz clock clean-up in timing-critical paths
ESD Rating (HBM)	5000 V - exceeds IEC 61000-4-2 Level 4, suitable for handheld and industrial field environments
Operating Temperature	−40 °C to +125 °C - qualified for under-hood automotive, industrial control, and outdoor IoT nodes

Pinout & Package

XSON8 package (SOT1203): 1.35 mm × 1.0 mm × 0.35 mm body, no leads, 8-terminal land-grid array with wettable flanks for automated optical inspection.

Pin/Terminal	Circuit Role	Design Meaning
1A, 2A	Input A for Gate 1 and Gate 2	Dual independent logic inputs accepting 0 V to 3.6 V; tolerant of overvoltage when VCC is unpowered
1B, 2B	Input B for Gate 1 and Gate 2	Schmitt-triggered inputs with hysteresis-reject noise on slow edges without external RC networks
1Y, 2Y	Output Y for Gate 1 and Gate 2	CMOS push-pull outputs sinking/sourcing ±4 mA at VCC = 3.0 V; IOFF disables output when VCC = 0 V
VCC	Positive Supply	Single rail powering both gates; IOFF circuitry activates automatically below ~0.2 V
GND	Ground Reference	Common return path for all inputs, outputs, and internal biasing; decoupling required within 2 mm

Key Features

Feature	Design Value
Wide-Voltage Schmitt Trigger	VT+ and VT− scale linearly with VCC-enables consistent noise margin across 0.8–3.6 V without recalibration
IOFF Partial Power-Down	Outputs enter high-Z state at VCC = 0 V, eliminating backfeed risk in hot-swap or multi-rail systems
Ultra-Low ICC	≤1.4 μA max over full temperature range-reduces quiescent power by >90% vs. standard AUP logic
High ESD Robustness	HBM 5000 V and CDM 1000 V-eliminates need for external TVS diodes in most board-level ESD designs
Thermal Performance	Ptot = 250 mW (SOT1203), derating 3.6 mW/K above 81 °C-supports continuous operation in sealed enclosures

Applications

Wave Shaping

Astable Multivibrator

Use Scenario: Converting noisy, slow-rising analog sensor outputs (e.g., thermistor divider, photodiode amplifier) into clean digital pulses for microcontroller GPIO capture.

IC Role / Device Role / Timing Role: Dual Schmitt NAND acts as edge cleaner and pulse stretcher-first gate shapes input, second gate inverts and sharpens output.

Use Value: Eliminates external RC filters and debounce firmware; reduces BOM count by one passive per channel while improving jitter tolerance.

Use Scenario: Generating precise, stable square-wave clocks (1 kHz–100 kHz) for LED drivers or sensor sampling where crystal oscillators are cost-prohibitive.

IC Role / Device Role / Timing Role: Cross-coupled configuration using both NAND gates and external R-C network forms self-oscillating relaxation oscillator.

Use Value: Achieves <±5% frequency stability over −40 °C to +85 °C with only two resistors and one capacitor-no trimming required.

Monostable Multivibrator

Industrial Pushbutton Debounce

Use Scenario: Creating fixed-duration output pulses (e.g., 50 ms–500 ms) from momentary switch closures in PLC I/O modules or safety interlocks.

IC Role / Device Role / Timing Role: Single NAND gate configured with RC feedback generates time-controlled output pulse; second gate provides inversion if needed.

Use Value: Pulse width set solely by external R and C-no software timer overhead, immune to MCU reset or interrupt latency.

Use Scenario: Conditioning mechanical switch inputs in factory HMIs or medical device control panels exposed to EMI and vibration.

IC Role / Device Role / Timing Role: Schmitt inputs reject contact bounce (1–10 ms) and conducted noise; IOFF allows safe integration into partially powered backplane slots.

Use Value: Guarantees single, glitch-free edge per press-reduces firmware validation effort and eliminates missed/phantom key events.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual Schmitt NAND applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC2G132DCUR	Wider VCC range (1.65–5.5 V); higher ICC (max 10 μA); no IOFF; LVC logic family	Requires ≥1.65 V supply; unsuitable for sub-1.2 V systems or partial power-down scenarios	Select when interfacing with 5 V legacy peripherals or when higher drive strength (24 mA) is needed
74LVC2G132GM,132	Same XQFN8 package (SOT902-2); identical pinout; IOFF supported; max ICC = 2.5 μA at +125 °C	Thermal resistance 120 K/W vs. 160 K/W for SOT1203-better for sustained >50 mW dissipation	Prefer for thermally constrained layouts requiring higher continuous power handling

Compared with SN74LVC2G132DCUR and 74LVC2G132GM,132, the 74AUP2G132GS,115 offers superior ultra-low-power operation below 1.2 V and guaranteed IOFF behavior-making it optimal for energy-harvesting nodes and modular systems with dynamic rail sequencing.

Availability

74AUP2G132GS,115 is available at Aetrix Electronics and suitable for wave shapers, astable multivibrators, monostable timers, and industrial pushbutton debounce circuits requiring stable component supply across automotive, industrial, and IoT product lifecycles.

Supply support for 74AUP2G132GS,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies-delivering high-performance, reliable logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) logic family targets battery-constrained and thermally sensitive applications, emphasizing sub-1 μA static current, scalable voltage operation, and robust IOFF functionality for modern mixed-domain systems.

FAQ

What is the minimum supply voltage at which 74AUP2G132GS,115 guarantees correct Schmitt-trigger operation?

The device is fully specified from 0.8 V to 3.6 V. At VCC = 0.8 V, VT+ = 0.30 V (min) and VT− = 0.10 V (min), providing 0.20 V hysteresis-sufficient to reject typical PCB noise. All DC and AC parameters, including IOFF activation, are guaranteed across this full range per JEDEC JESD8-12.

Can 74AUP2G132GS,115 be used with 3.3 V inputs while operating at 1.8 V VCC?

Yes. Inputs are overvoltage tolerant up to 3.6 V regardless of VCC level. When VCC = 1.8 V, VI(max) = 3.6 V is explicitly permitted, and the IOFF circuit remains active if VCC drops to 0 V-making it safe for level-shifting between 3.3 V sensors and 1.8 V microcontrollers without external components.

How does the IOFF feature behave during power sequencing in a multi-rail system?

IOFF activates automatically when VCC falls below ~0.2 V, forcing outputs into high-impedance state before supply collapse. This prevents back-driving powered rails through the outputs-a critical safeguard during staggered power-up/down of FPGA I/O banks, PMIC domains, or hot-pluggable modules.

Is the SOT1203 (XSON8) package compatible with standard reflow profiles for lead-free assembly?

Yes. The SOT1203 package is qualified for IPC/JEDEC J-STD-020 moisture sensitivity level 1 (MSL1) and withstands peak reflow temperatures up to 260 °C. Its 0.35 mm profile and wettable flanks support automated optical inspection and high-yield placement in fine-pitch SMT lines.

74AUP2G132GS,115 Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: *

Package/Case:: -

Packaging:: Bulk

Product Status:: Active

Logic Type:: -

Number of Circuits:: -

Number of Inputs:: -

Features:: -

Voltage - Supply:: -

Current - Quiescent (Max):: -

Current - Output High, Low:: -

Input Logic Level - Low:: -

Input Logic Level - High:: -

Max Propagation Delay @ V, Max CL:: -

Operating Temperature:: -

Grade:: -

Qualification:: -

Mounting Type:: -

Supplier Device Package:: -

74AUP2G132GS,115 FAQ

1.How can I place an order for 74AUP2G132GS,115 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AUP2G132GS,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AUP2G132GS,115 reliable?

The price and inventory of 74AUP2G132GS,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G132GS,115 is usually 5 days.

3.What payment methods are accepted for 74AUP2G132GS,115?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP2G132GS,115 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74AUP2G132GS,115?

74AUP2G132GS,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74AUP2G132GS,115 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74AUP2G132GS,115?

For technical support, including 74AUP2G132GS,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G132GS,115 requirements.

6.How does Aetrix verify that 74AUP2G132GS,115 is sourced from the original manufacturer or authorized distributors?

All 74AUP2G132GS,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G132GS,115 meets industry standards.

7.What is the process for return or replacement of 74AUP2G132GS,115?

All 74AUP2G132GS,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G132GS,115, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AUP2G132GS,115 part is unused and in its original packaging.

Return procedure for 74AUP2G132GS,115:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

2026-08-11 LDO Regulator: Dropout Voltage, Noise, PSRR and Power Dissipation

LDO regulator guide covering low dropout voltage, power dissipation, thermal design, PSRR, output noise, capacitor stability, adjustable LDO circuits, LDO vs buck converter and datasheet selection chec…

2026-08-06 Conditional Access Module: CAM, CI/CI+ and DVB Security

Conditional Access Module guide covering CAM meaning, CI/CI+ interface, smart card authorization, DVB security workflow, TV and set-top box compatibility, internal electronics, ESD protection, connecto…

2026-08-03 Electronic Component Obsolescence: EOL Risks, Replacement Options and Last-Time Buy Strategy

Guide to electronic component obsolescence covering EOL risk, PCN/PDN notices, last-time buy planning, replacement options, form-fit-function validation, counterfeit risk and BOM lifecycle management.

2026-07-29 18650 Battery: Voltage, Capacity, Charging and Pack Design

18650 battery guide covering lithium-ion cell basics, 3.6V/3.7V voltage, 4.2V charging, mAh and Wh capacity, protected cells, chargers, BMS, series-parallel packs, holders, welding and sourcing checks.…

2026-07-27 Hall Effect Sensor: Working Principle, Types, Circuits and Applications

Hall effect sensor guide covering working principle, linear and digital sensors, Arduino circuits, current sensing, speed detection, automotive applications, A3144 examples, signal filtering and datash…

2026-07-20 Product Change Notification (PCN) in Electronic Components: Meaning and Supply Chain Response

Product Change Notification guide for electronic components, covering PCN meaning, PCN vs PDN/EOL, common change types, risk levels, form-fit-function review, engineering validation, BOM control, LTB/L…

2026-07-19 Blend Door Actuator: Symptoms, Location, Reset and Replacement Guide

A practical guide to blend door actuators, covering HVAC function, symptoms, location, AC and heater issues, reset and calibration, replacement cost, electrical diagnosis, compatibility checks, and rep…

2026-07-17 Raspberry Pi Alternatives: Chip-Level Comparison, Compatibility and Replacement Guide

Engineering guide to Raspberry Pi alternatives, covering chip-level differences, Orange Pi, ROCK, Jetson, Banana Pi, NanoPi, Compute Module, Pico, GPIO, camera, HAT compatibility, and replacement risks…