Nexperia USA Inc. 74AUP2G132GT,115
- Part No.:
- 74AUP2G132GT,115
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Gates and Inverters
- Package:
- 8-XFDFN
- Datasheet:
-
74AUP2G132GT,115.pdf
- Description:
- IC GATE NAND 2CH 2-INP 8XSON
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74AUP2G132GT,115 from Nexperia is a dual 2-input NAND gate with Schmitt-trigger inputs, designed for noise-immune signal conditioning in ultra-low-power systems operating from 0.8 V to 3.6 V. It features IOFF partial power-down protection, <0.9 μA max ICC at 125 °C, 8-terminal XSON8 (SOT833-1) package, and supports wave shaping and multivibrator circuits in battery-powered IoT sensors and portable medical monitors.
For engineers reviewing the 74AUP2G132GT,115 datasheet, 74AUP2G132GT,115 pinout, 74AUP2G132GT,115 application, or 74AUP2G132GT,115 equivalent, key selection criteria include Schmitt-trigger hysteresis (0.79–1.31 V at 3.0 V), propagation delay as low as 1.4 ns at 3.0 V/CL=5 pF, IOFF leakage ≤±0.75 μA at VCC = 0 V, and guaranteed operation from –40 °C to +125 °C in XSON8 thermal profile.
Technical Context
This device implements two independent NAND logic gates, each with asymmetric Schmitt-trigger input thresholds (VT+ = 1.88–2.32 V, VT– = 0.88–1.24 V at VCC = 3.0 V) enabling robust noise rejection on slow-rising signals. The IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V while inputs/outputs remain biased up to 3.6 V.
It complies with JEDEC standards JESD8-12 through JESD8C across five voltage bands and meets HBM ESD >5000 V and CDM >1000 V. Dynamic performance is characterized at CL = 5–30 pF and VCC = 0.8–3.6 V, with tpd scaling inversely with supply voltage and load capacitance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Function | Dual 2-input NAND with Schmitt-trigger inputs - enables clean digital output from noisy or slow analog-like waveforms |
| Supply Voltage Range | 0.8 V to 3.6 V - supports single-supply operation across 1.0 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V system rails |
| Max ICC (Tamb = –40 °C to +125 °C) | 1.4 μA - ensures sub-microwatt static power in always-on sensor nodes and wearables |
| Hysteresis Voltage (VH) | 0.79–1.31 V at VCC = 3.0 V - provides ≥400 mV noise margin against EMI in industrial control feedback paths |
| tpd (VCC = 3.0 V, CL = 5 pF) | 1.4–6.2 ns - delivers nanosecond timing resolution for pulse edge detection in encoder interfaces |
| IOFF Leakage (VCC = 0 V) | ±0.75 μA - prevents cross-conduction and bus contention in hot-swap and multi-rail power sequencing |
| Operating Temperature | –40 °C to +125 °C - qualified for under-hood automotive, motor drive control, and industrial PLC modules |
Pinout & Package
XSON8 plastic extremely thin small outline package (SOT833-1); no leads; 8 terminals; body dimensions 1.0 mm × 1.95 mm × 0.5 mm; thermal pad omitted; pin 1 indicator located below marking code in lower-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1A | First NAND gate input A - accepts overvoltage-tolerant signals up to 3.6 V independent of VCC |
| 2 | 1B | First NAND gate input B - Schmitt-trigger threshold ensures reliable switching despite slow rise/fall times |
| 3 | 1Y | First NAND gate output Y - drives capacitive loads ≤30 pF with defined VOH/VOL across full VCC range |
| 4 | GND | Ground reference - common return path for all internal logic and I/O; must be low-impedance |
| 5 | 2A | Second NAND gate input A - electrically isolated from 1A; enables dual independent signal conditioning |
| 6 | 2B | Second NAND gate input B - shares same Schmitt characteristics and voltage tolerance as 1B |
| 7 | 2Y | Second NAND gate output Y - supports concurrent waveform shaping without crosstalk |
| 8 | VCC | Supply voltage - powers both gates; IOFF activates automatically when VCC = 0 V |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range | 0.8 V to 3.6 V enables direct interface with energy-harvesting PMUs and multi-voltage SoCs |
| IOFF partial power-down | Prevents damaging backflow current during VCC ramp-down, critical for FPGA I/O bank isolation |
| High noise immunity | Input hysteresis ≥0.79 V at 3.0 V suppresses false triggering from EFT bursts in motor control encoders |
| Low dynamic power | CPD = 4.4 pF at 3.3 V minimizes switching loss in high-frequency clock cleanup applications |
| Overvoltage-tolerant inputs | Accepts 3.6 V signals even at VCC = 0.8 V - simplifies level-shifting in mixed-voltage sensor hubs |
Applications
| Wave Shaper | Astable Multivibrator |
|---|---|
Use Scenario: Converting noisy sine or triangle waves from MEMS accelerometers into clean square-wave clock signals for microcontroller capture timers. IC Role / Device Role / Timing Role: Dual NAND gate configured as Schmitt-trigger inverter pair to regenerate digital edges with precise hysteresis-controlled thresholds. Use Value: Eliminates need for external RC networks and discrete comparators, reducing BOM count by 3 components per channel while maintaining ±50 mV noise margin. | Use Scenario: Generating fixed-frequency clock signals for LED blink patterns or status indicators in battery-powered handheld diagnostics tools. IC Role / Device Role / Timing Role: Cross-coupled NAND configuration forming self-oscillating relaxation oscillator with frequency set by external R/C network. Use Value: Achieves stable 1–100 kHz oscillation using only two resistors and one capacitor, consuming <2 μA quiescent current at 1.8 V supply. |
| Monostable Multivibrator | Power Sequencing Monitor |
Use Scenario: Creating precise pulse-width-limited wake-up triggers for ultra-low-power microcontrollers responding to mechanical switch bounce or button press events. IC Role / Device Role / Timing Role: Single NAND gate used in edge-triggered monostable configuration with RC timing network defining output pulse duration. Use Value: Delivers jitter-free 10–500 ms pulses with <±3% tolerance over temperature, replacing discrete 555-based designs that draw >100× more current. | Use Scenario: Validating correct power-up sequence of multiple rails (e.g., 1.2 V core before 3.3 V I/O) in FPGA carrier boards before releasing reset. IC Role / Device Role / Timing Role: NAND gate acting as active-low enable detector, asserting "power OK" only when all monitored supplies exceed their Schmitt thresholds. Use Value: Provides rail-order validation with built-in hysteresis, eliminating external window comparators and reducing startup verification time by 40%. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual Schmitt NAND gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G132DCUR | Wider VCC range (1.65–5.5 V); higher ICC (max 10 μA); no IOFF; SOT23-8 package | Requires ≥1.65 V supply; unsuitable for partial power-down systems; larger footprint | Select when interfacing with 5 V legacy peripherals and IOFF is not required |
| 74LVC2G132GM,132 | Same XSON8 footprint; identical Schmitt thresholds; IOFF supported; but rated only to +85 °C | Limited to commercial/industrial ambient; not qualified for automotive under-hood use | Select for cost-sensitive consumer electronics where extended temperature is unnecessary |
Compared with SN74LVC2G132DCUR and 74LVC2G132GM,132, the 74AUP2G132GT,115 uniquely combines sub-μA static current, –40 °C to +125 °C qualification, and IOFF in the smallest XSON8 footprint-making it optimal for thermally constrained, battery-critical, and automotive-grade designs.
Availability
74AUP2G132GT,115 is available at Aetrix Electronics and suitable for battery-powered IoT sensors, automotive body control modules, and portable medical monitors requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74AUP2G132GT,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable, and efficient logic, discrete, and MOSFET solutions with leadership in process technology and application-specific optimization.
The 74AUP (Advanced Ultra-low Power) product line targets energy-constrained applications such as wearables, wireless sensors, and automotive subsystems where nanowatt static power and robust noise immunity are mandatory design requirements.
FAQ
What is the minimum supply voltage for guaranteed operation of the 74AUP2G132GT,115?
The 74AUP2G132GT,115 is fully specified from 0.8 V to 3.6 V. At 0.8 V, it maintains functional logic behavior with tpd ≤22.5 ns (CL = 5 pF) and VIH/VIL thresholds scaled proportionally. All DC and AC parameters-including Schmitt hysteresis and IOFF-are guaranteed across this full range per JEDEC JESD8-12 compliance.
How does the IOFF feature protect the device during partial power-down?
When VCC = 0 V, the IOFF circuitry disables both outputs (1Y and 2Y), presenting high-impedance states regardless of input voltage (up to 3.6 V). This prevents reverse current flow from powered I/O lines into the unpowered IC, eliminating latch-up risk and ensuring safe hot-plug operation in modular systems with staggered power domains.
Can the 74AUP2G132GT,115 drive a 30 pF load at 3.0 V with sub-10 ns propagation delay?
Yes. At VCC = 3.0 V and CL = 30 pF, the maximum tpd is 10.1 ns (–40 °C to +125 °C), with typical value 7.8 ns. The device sustains this performance while maintaining VOH ≥2.30 V and VOL ≤0.50 V under 4 mA load, meeting timing closure for 100 MHz clock edge sampling in low-pin-count microcontrollers.
Is the XSON8 (SOT833-1) package compatible with standard reflow profiles for lead-free assembly?
Yes. The SOT833-1 package is qualified for IPC/JEDEC J-STD-020D moisture sensitivity level 1 (MSL1) and supports peak reflow temperatures up to 260 °C. Its 0.5 mm body height and 0.4 mm terminal pitch are compatible with standard 0201-class stencil apertures and automated optical inspection (AOI) systems used in high-volume SMT lines.
74AUP2G132GT,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 8-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- NAND Gate
- Number of Circuits:
- 2
- Number of Inputs:
- 2
- Features:
- Schmitt Trigger
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Max):
- 500 nA
- Current - Output High, Low:
- 4mA, 4mA
- Input Logic Level - Low:
- 0.1V ~ 0.88V
- Input Logic Level - High:
- 0.6V ~ 2.29V
- Max Propagation Delay @ V, Max CL:
- 7.8ns @ 3.3V, 30pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XSON, SOT833-1 (1.95x1)
74AUP2G132GT,115 FAQ
1.How can I place an order for 74AUP2G132GT,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G132GT,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G132GT,115 reliable?
The price and inventory of 74AUP2G132GT,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G132GT,115 is usually 5 days.
3.What payment methods are accepted for 74AUP2G132GT,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP2G132GT,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP2G132GT,115?
74AUP2G132GT,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP2G132GT,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G132GT,115?
For technical support, including 74AUP2G132GT,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G132GT,115 requirements.
6.How does Aetrix verify that 74AUP2G132GT,115 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G132GT,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G132GT,115 meets industry standards.
7.What is the process for return or replacement of 74AUP2G132GT,115?
All 74AUP2G132GT,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G132GT,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G132GT,115 part is unused and in its original packaging.
Return procedure for 74AUP2G132GT,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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