Nexperia USA Inc. 74AUP2G14GF,132
- Part No.:
- 74AUP2G14GF,132
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Gates and Inverters
- Package:
- 6-XFDFN
- Datasheet:
-
74AUP2G14GF,132.pdf
- Description:
- IC INVERT SCHMITT 2CH 2INP 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:3,590
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Product details
Overview
74AUP2G14GF,132 from Nexperia is a dual Schmitt-trigger inverter IC designed for low-power signal conditioning in battery-powered and space-constrained systems. It operates across 0.8 V to 3.6 V supply, delivers ≤0.9 μA max ICC at 125 °C, features IOFF partial power-down protection, and supports −40 °C to +125 °C operation in SOT886 (XSON6) package.
For engineers reviewing the 74AUP2G14GF,132 datasheet, 74AUP2G14GF,132 pinout, 74AUP2G14GF,132 application, or 74AUP2G14GF,132 equivalent, key selection criteria include Schmitt-trigger hysteresis (min 0.07 V at 0.8 V VCC), propagation delay down to 1.5 ns at 3.0 V/CL=5 pF, overvoltage-tolerant inputs up to 3.6 V, and IOFF-enabled isolation during system power sequencing.
Technical Context
This device implements two independent CMOS inverters with Schmitt-trigger inputs-each providing hysteresis (VH = VT+ − VT−) to reject noise on slow-rising/falling signals. Thresholds are supply-dependent: VT+ ranges from 0.30 V (0.8 V VCC) to 2.32 V (3.0 V VCC); VT− from 0.10 V to 1.24 V.
The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA max, enabling safe hot-insertion and multi-rail partial power-down. Input clamping and ESD robustness (HBM >5 kV, CDM >1 kV) support rugged industrial interfacing without external protection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 0.8 V to 3.6 V - Enables direct interface with 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| ICC (max) | 1.4 μA at −40 °C to +125 °C - Ensures sub-μA static power in always-on sensor nodes or real-time clock backup paths. |
| tPD (min) | 1.5 ns at VCC = 3.0 V, CL = 5 pF - Supports clean edge generation for clockless timing circuits up to ~330 MHz toggle rate. |
| VH (hysteresis) | 0.07 V to 1.31 V - Provides noise margin scalable with supply; e.g., 0.79 V at 3.0 V enables reliable recovery from ≥26% amplitude noise. |
| IOFF Leakage | ±0.75 μA max at VCC = 0 V - Prevents cross-talk and bus contention when one subsystem powers down while others remain active. |
| ESD Rating | HBM >5000 V, CDM >1000 V - Eliminates need for external TVS diodes in handheld or exposed I/O applications. |
| Operating Temp | −40 °C to +125 °C - Qualified for under-hood automotive, industrial motor control, and outdoor IoT deployments. |
Pinout & Package
SOT886 (XSON6) package: plastic extremely thin small outline, no leads, 6 terminals, body size 1.0 mm × 1.45 mm × 0.5 mm, thermal pad optional, moisture sensitivity level 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1A | First inverter input - Schmitt-triggered; accepts overvoltage up to 3.6 V regardless of VCC. |
| 2 | GND | Digital ground reference - Must be low-impedance; shared return for both inverters and IOFF control path. |
| 3 | 2A | Second inverter input - Electrically isolated from 1A; enables dual independent signal conditioning. |
| 4 | 2Y | Second inverter output - CMOS push-pull; drives capacitive loads ≤30 pF with <4.7 ns tPD at 3.0 V. |
| 5 | VCC | Supply voltage input - Powers both inverters and IOFF logic; decoupling capacitor required within 2 mm. |
| 6 | 1Y | First inverter output - Matches 2Y electrically; allows cascaded or parallel use without skew concerns. |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range | 0.8 V–3.6 V operation enables single BOM across multiple voltage rails (e.g., 1.2 V core + 3.3 V I/O). |
| IOFF partial power-down | Active output disable at VCC = 0 V prevents backfeed into powered sections during hot-swap or sleep mode. |
| Overvoltage-tolerant inputs | Inputs withstand 3.6 V even at VCC = 0.8 V - simplifies mixed-voltage signal routing without translators. |
| Low dynamic noise | Overshoot/undershoot <10% of VCC - reduces EMI in sensitive RF or analog-adjacent PCB layouts. |
| High noise immunity | Input hysteresis ≥0.5 V typical at 1.8 V VCC - rejects burst noise and contact bounce in mechanical switch debouncing. |
Applications
| Wave and pulse shaper | Astable multivibrator |
|---|---|
Use Scenario: Converting noisy or slow-rising analog sensor outputs (e.g., thermistor divider, photodiode amplifier) into clean digital edges for MCU GPIO capture. IC Role / Device Role / Timing Role: Dual Schmitt-trigger inverter - first stage cleans input; second stage provides rail-to-rail square wave output with controlled rise/fall. Use Value: Eliminates external RC filters and comparator bias networks; reduces BOM count by 3–4 passive components per channel. | Use Scenario: Generating precise, temperature-stable clock signals for LED blinkers, status indicators, or low-frequency timers where crystal accuracy is unnecessary. IC Role / Device Role / Timing Role: Cross-coupled inverter pair with external R-C network - forms self-oscillating relaxation oscillator with duty cycle tunable via resistor ratio. Use Value: Achieves <±5% frequency stability from −40 °C to +85 °C using only two resistors and one capacitor; no crystal load or startup delay. |
| Monostable multivibrator | Power sequencing supervisor |
Use Scenario: Creating fixed-duration pulses from momentary button presses or asynchronous interrupt signals in wearables and portable medical devices. IC Role / Device Role / Timing Role: One inverter plus RC differentiator - converts edge into pulse width defined by R×C time constant; second inverter buffers output. Use Value: Pulse width adjustable from 10 μs to 100 ms with standard 1% resistors and NP0 capacitors; no external op-amp or timer IC required. | Use Scenario: Monitoring power-good status of multiple rails (e.g., 1.2 V core, 3.3 V I/O) and asserting a consolidated reset signal to an MCU during brown-out conditions. IC Role / Device Role / Timing Role: Inverter with pull-up on input - used as level translator and edge detector; IOFF ensures no leakage when main VCC drops before auxiliary supplies. Use Value: Enables fail-safe power sequencing without dedicated supervisor IC; maintains isolation between unpowered and powered domains during ramp-down. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual Schmitt-trigger inverter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G14DSFR | Wider VCC range (1.65 V–5.5 V); higher ICC (10 μA typ); no IOFF; 6-pin WSON package (same footprint as SOT886). | Lacks partial power-down capability; unsuitable for multi-rail hot-swap systems requiring backflow prevention. | Select when interfacing with 5 V logic or when IOFF is not required; verify VIH/VIL compatibility at lower VCC. |
| 74LVC2G14GW,125 | Same SOT363-2 (TSSOP6) package; identical pinout; IOFF supported; but ICC = 4 μA max at 125 °C (vs. 1.4 μA). | Higher static power limits use in ultra-low-power battery applications (>10-year shelf life). | Select when board layout requires leaded package or reworkability; accept 3× higher quiescent current for legacy assembly compatibility. |
Compared with SN74LVC2G14DSFR and 74LVC2G14GW,125, the 74AUP2G14GF,132 uniquely combines sub-μA ICC, IOFF, and overvoltage-tolerant inputs in a 1.0 mm × 1.45 mm XSON6 package-making it optimal for miniaturized, multi-rail, long-life embedded systems.
Availability
74AUP2G14GF,132 is available at Aetrix Electronics and suitable for battery-powered sensors, automotive body controllers, and industrial HMI interfaces requiring stable component supply across extended temperature and voltage ranges.
Supply support for 74AUP2G14GF,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, with leadership in energy-efficient and space-saving packaging technologies.
The 74AUP (Advanced Ultra Low Power) logic family targets ultra-low-power portable and always-on applications, emphasizing minimal ICC, wide VCC scalability, and robust IO architecture for modern mixed-signal systems.
FAQ
What is the maximum input voltage the 74AUP2G14GF,132 can tolerate when VCC = 0.8 V?
The inputs are overvoltage tolerant up to 3.6 V regardless of VCC level. This is confirmed in Section 2 (Features and benefits) and Table 5 (Limiting values), where VI (input voltage) is rated −0.5 V to +4.6 V, and explicitly stated as "Overvoltage tolerant inputs to 3.6 V" - enabling safe interfacing with higher-voltage peripherals without level shifters.
Does the 74AUP2G14GF,132 support true bidirectional signal translation?
No. It is a unidirectional inverter with Schmitt-trigger inputs and CMOS push-pull outputs. While inputs tolerate 3.6 V at low VCC, the outputs swing only between GND and the applied VCC (0.8 V–3.6 V). Bidirectional level translation requires dedicated translators like NXSL0108 or TXB0108.
Can the 74AUP2G14GF,132 be used to debounce mechanical switches directly?
Yes. Its Schmitt-trigger inputs provide inherent hysteresis (e.g., 0.79 V at 3.0 V VCC), and its low ICC (<1.4 μA) minimizes switch leakage impact. A simple RC filter (e.g., 100 kΩ + 100 nF) at the input suffices for reliable debouncing - verified in Application Note AN10787 and Fig. 14 (Relaxation oscillator) showing robust response to slow edges.
Is thermal pad connection required for the SOT886 package?
No. The SOT886 (XSON6) package does not include an exposed thermal pad; its thermal performance relies on solder connections at the six perimeter terminals. Datasheet Figure 16 shows no thermal pad feature, and Ptot derating (3.3 mW/K above 74 °C) assumes standard PCB copper land patterns without thermal vias.
74AUP2G14GF,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Inverter
- Number of Circuits:
- 2
- Number of Inputs:
- 2
- Features:
- Schmitt Trigger
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Max):
- 500 nA
- Current - Output High, Low:
- 4mA, 4mA
- Input Logic Level - Low:
- 0.1V ~ 0.88V
- Input Logic Level - High:
- 0.6V ~ 2.29V
- Max Propagation Delay @ V, Max CL:
- 6.1ns @ 3.3V, 30pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT891 (1x1)
74AUP2G14GF,132 FAQ
1.How can I place an order for 74AUP2G14GF,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AUP2G14GF,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AUP2G14GF,132 reliable?
The price and inventory of 74AUP2G14GF,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AUP2G14GF,132 is usually 5 days.
3.What payment methods are accepted for 74AUP2G14GF,132?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AUP2G14GF,132 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74AUP2G14GF,132?
74AUP2G14GF,132 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AUP2G14GF,132 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AUP2G14GF,132?
For technical support, including 74AUP2G14GF,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AUP2G14GF,132 requirements.
6.How does Aetrix verify that 74AUP2G14GF,132 is sourced from the original manufacturer or authorized distributors?
All 74AUP2G14GF,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AUP2G14GF,132 meets industry standards.
7.What is the process for return or replacement of 74AUP2G14GF,132?
All 74AUP2G14GF,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74AUP2G14GF,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AUP2G14GF,132 part is unused and in its original packaging.
Return procedure for 74AUP2G14GF,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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