Nexperia USA Inc. 74AUP2G14GS,132

Overview

74AUP2G14GS,132 from Nexperia is a dual Schmitt-trigger inverter IC designed for low-power signal conditioning in battery-sensitive and noise-prone digital systems. It operates across 0.8 V to 3.6 V supply, delivers ≤1.4 μA max ICC at −40 °C to +125 °C, features IOFF partial power-down protection, and supports 6-terminal XSON6 (SOT1202) packaging with 1.0 × 1.0 × 0.35 mm footprint - used in waveform shaping and relaxation oscillator circuits.

For engineers reviewing the 74AUP2G14GS,132 datasheet, 74AUP2G14GS,132 pinout, 74AUP2G14GS,132 application, or 74AUP2G14GS,132 equivalent, key selection criteria include its Schmitt-trigger hysteresis (0.79–1.31 V at VCC = 3.0 V), ultra-low static current, IOFF-enabled system-level power sequencing, and compatibility with 1.0 mm × 1.0 mm space-constrained PCB layouts.

Technical Context

This device implements two independent CMOS inverters with Schmitt-trigger inputs, enabling clean digital signal regeneration from slow-rising or noisy analog-like waveforms. Its input thresholds (VT+ = 1.88–2.32 V, VT− = 0.88–1.24 V at VCC = 3.0 V) provide ≥0.79 V hysteresis, ensuring robust noise immunity in industrial sensor interfaces and clock recovery paths.

The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±0.75 μA and supporting hot-swap and partial power-down architectures. Propagation delay ranges from 1.5 ns (VCC = 3.0 V, CL = 5 pF) to 7.4 ns (VCC = 3.0 V, CL = 30 pF), maintaining timing predictability across voltage and temperature extremes.

Key Specifications

Pinout & Package

XSON6 package (SOT1202): 6-terminal, leadless, 1.0 mm × 1.0 mm × 0.35 mm body with exposed thermal pad; optimized for high-density routing and thermal performance in compact portable designs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual Schmitt-trigger inverter applications.

Compared with SN74LVC2G14DBVR and 74LVC2G14GW,125, the 74AUP2G14GS,132 offers superior ultra-low-power operation (1.4 μA vs. 10 μA), smallest footprint (1.0 mm²), and guaranteed IOFF behavior - making it optimal for space- and energy-constrained edge devices where power sequencing integrity is critical.

Availability

74AUP2G14GS,132 is available at Aetrix Electronics and suitable for waveform shaping, relaxation oscillator generation, monostable timing, and industrial switch debouncing requiring stable component supply across automotive, industrial, and portable electronics programs.

Supply support for 74AUP2G14GS,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions for automotive, industrial, and mobile markets.

The 74AUP (Advanced Ultra-low Power) product line targets battery-powered and thermally constrained applications demanding nanowatt static power, wide voltage operation, and robust ESD performance - exemplified by the 74AUP2G14GS,132's 0.8–3.6 V range and 1.4 μA max ICC.

FAQ

Does 74AUP2G14GS,132 support true bidirectional signal conditioning?

No - it is a unidirectional dual inverter with fixed input (1A/2A) and output (1Y/2Y) terminals. Each channel operates strictly as an inverting buffer with Schmitt-trigger input; no internal feedback or configurable direction control is provided. Signal flow is strictly input→output per channel.

What is the maximum capacitive load this device can drive reliably?

The device is characterized up to 30 pF load capacitance, with propagation delay specified at CL = 5, 10, 15, and 30 pF. Driving >30 pF may increase tpd unpredictably and raise dynamic power; for heavier loads, a dedicated buffer stage is recommended per Nexperia's application guidance.

Can the IOFF feature be used with VCC = 0 V while inputs remain at 3.3 V?

Yes - the IOFF circuit remains active when VCC = 0 V, and inputs tolerate up to 3.6 V regardless of supply state. Input leakage is limited to ±0.75 μA, and output is high-impedance, preventing backfeed into powered sections - validated per JESD78B Class II latch-up testing.

How does the Schmitt-trigger threshold vary with temperature and supply voltage?

At VCC = 3.0 V, VT+ ranges from 1.88 V (min, −40 °C) to 2.32 V (max, +125 °C); VT− ranges from 0.88 V (min) to 1.24 V (max). Hysteresis (VT+ − VT−) stays within 0.79–1.31 V across full temperature and voltage range, ensuring consistent noise margin in all operating conditions.