Nexperia USA Inc. 74AUP2G157DC,125

Overview

74AUP2G157DC,125 from Nexperia is a low-power 2-input multiplexer IC with true/complement outputs (Y/Y̅), active-low enable (E), and Schmitt-trigger inputs for noise immunity across 0.8 V–3.6 V supply. It selects between I0/I1 under S control, supports partial power-down via IOFF, and operates from –40 °C to +125 °C in VSSOP8 package - used in battery-powered sensor interfaces and level-shifting data routing.

For engineers reviewing the 74AUP2G157DC,125 datasheet, 74AUP2G157DC,125 pinout, 74AUP2G157DC,125 application, or 74AUP2G157DC,125 equivalent, key selection criteria include its ultra-low ICC (≤1.4 μA), dual-output logic format, IOFF-enabled power sequencing, and VSSOP8 footprint compatibility with space-constrained PCB layouts.

Technical Context

This device implements a single-pole double-throw (SPDT) analog/digital signal selector with complementary outputs, where the enable input (E) forces Y = LOW and Y̅ = HIGH when asserted HIGH. Its Schmitt-trigger inputs tolerate slow edges and ensure clean switching across the full 0.8 V–3.6 V VCC range.

The IOFF circuit disables both outputs during power-down, blocking backflow current when VCC = 0 V while inputs/outputs remain biased at 0–3.6 V - critical for hot-swap and multi-rail system interoperability. Propagation delays range from 1.0 ns (VCC = 3.3 V, CL = 5 pF) to 38.8 ns (VCC = 0.8 V, CL = 30 pF) depending on load and voltage.

Key Specifications

Pinout & Package

VSSOP8 plastic very thin shrink small outline package (SOT765-1); 8 leads; body width 2.3 mm; pin 1 indicator located below marking code 'a2P' in lower-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input multiplexer applications.

Compared with SN74LVC2G157DCUR and 74LVC1G157GW,125, the 74AUP2G157DC,125 uniquely combines ultra-low ICC, IOFF, true/complement outputs, and 0.8 V operation - making it optimal for energy-critical, multi-voltage, and hot-plug-capable designs.

Availability

74AUP2G157DC,125 is available at Aetrix Electronics and suitable for industrial sensor hubs, automotive body control modules, wearable health monitors, and smart home hub interfaces requiring stable component supply across extended temperature ranges and low-power operation.

Supply support for 74AUP2G157DC,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a leading semiconductor manufacturer specializing in high-performance, energy-efficient logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and thermally constrained applications where sub-microamp quiescent current, wide VCC flexibility, and robust IOFF behavior are mandatory design requirements.

FAQ

What is the maximum allowable input voltage when VCC = 0 V?

The 74AUP2G157DC,125 permits input voltages from 0 V to 3.6 V regardless of VCC state, enabled by its IOFF circuitry. This allows safe interfacing with live buses during power-down sequences - critical for hot-swap and multi-rail system designs where upstream sources remain active while the IC is unpowered.

Does this device support level translation between different VCC domains?

Yes - the 74AUP2G157DC,125 accepts input voltages up to 3.6 V independent of VCC (0.8 V–3.6 V), and outputs swing rail-to-rail relative to its own VCC. This enables bidirectional level shifting: e.g., a 3.3 V controller can safely drive I0/I1 while the IC runs at 1.8 V, with Y/Y̅ outputs referenced to 1.8 V.

How does the Schmitt-trigger input improve noise immunity?

Schmitt-trigger inputs provide hysteresis - typically >150 mV at 1.8 V - meaning the rising and falling thresholds differ significantly. This prevents multiple output transitions caused by slow-rising or noisy control signals (e.g., long PCB traces in motor drives), ensuring clean, single-event switching even with edge rates as low as 200 ns/V.

Can the true and complement outputs drive separate loads simultaneously?

Yes - Y and Y̅ are independently buffered outputs capable of driving separate CMOS loads up to ±4 mA each. Their complementary nature allows direct connection to differential receivers or cross-coupled logic gates without external inversion, reducing component count and propagation delay in timing-critical paths.