Nexperia USA Inc. 74AUP2G157GN,115

Overview

74AUP2G157GN,115 from Nexperia is a low-power 2-input multiplexer in XSON8 package (SOT1116), selecting between I0 and I1 under control of S and E inputs, delivering true (Y) and complement (Y) outputs with Schmitt-trigger inputs, ICC ≤ 1.4 μA at VCC = 0.8–3.6 V, −40 °C to +125 °C operation, and IOFF-enabled partial power-down for battery-powered sensor interfaces.

For engineers reviewing the 74AUP2G157GN,115 datasheet, 74AUP2G157GN,115 pinout, 74AUP2G157GN,115 application, or 74AUP2G157GN,115 equivalent, this device supports ultra-low-voltage signal routing in space-constrained IoT edge nodes, wearables, and portable instrumentation where supply voltage scalability, static current budgeting, and bus isolation during sleep mode are critical selection criteria.

Technical Context

The 74AUP2G157GN implements a single-pole double-throw (SPDT) analog/digital signal selector with active-low enable (E) and data-select (S) logic controlling output state. Its dual-output architecture delivers complementary Y/Y signals simultaneously, eliminating need for external inverters in differential signaling paths.

Schmitt-trigger inputs ensure robust noise immunity across full 0.8 V–3.6 V VCC range, while IOFF circuitry blocks backflow current when VCC = 0 V, enabling hot-swap and multi-rail system partitioning without latch-up risk per JESD78 Class II (>100 mA).

Key Specifications

Pinout & Package

XSON8 package (SOT1116): extremely thin small outline, no leads, 8-terminal surface-mount, body dimensions 1.2 mm × 1.0 mm × 0.35 mm, pin 1 indicator located below marking code 'aP' in lower-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input multiplexer applications.

Compared with SN74LVC2G157DCTR and 74LVC1G157GW,125, the 74AUP2G157GN,115 uniquely combines ultra-low ICC, IOFF, and true/complement outputs in a 1.2 mm × 1.0 mm XSON8 package - making it optimal for energy-critical, space-limited, and multi-power-domain designs where signal integrity and power-state coordination are non-negotiable.

Availability

74AUP2G157GN,115 is available at Aetrix Electronics and suitable for industrial sensor hubs, wearable biometric front-ends, and automotive body control modules requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AUP2G157GN,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency.

The 74AUP (Advanced Ultra-low Power) product line targets battery-operated and thermally constrained applications, emphasizing sub-μA static current, wide VCC scalability, and robust IOFF behavior for modern embedded systems.

FAQ

What is the maximum load capacitance supported without violating propagation delay specs?

The datasheet specifies tpd performance up to CL = 30 pF across all VCC and temperature conditions. At VCC = 3.3 V and Tamb = 25 °C, tpd remains ≤ 7.3 ns with CL = 30 pF. For CL > 30 pF, propagation delay increases linearly and must be validated per application; layout parasitics should be minimized to stay within timing budgets.

Can the 74AUP2G157GN,115 be used with 0.8 V logic levels while driving a 3.3 V load?

No - the device does not translate voltage levels. Its outputs swing between GND and VCC. To drive a 3.3 V load from a 0.8 V VCC supply, an external level shifter is required. However, inputs tolerate up to 3.6 V regardless of VCC, enabling connection to higher-voltage control signals.

How does the IOFF feature behave when VCC is ramping during power-up?

IOFF activates when VCC falls below ~0.2 V and remains active until VCC exceeds ~0.5 V. During power-up, outputs remain isolated until VCC stabilizes above the functional threshold. This prevents glitching or backfeeding during brownout recovery, provided external pull-downs/pull-ups are sized to avoid contention.

Is the Y/Y output pair guaranteed to switch simultaneously?

Yes - the internal logic ensures matched propagation delays between Y and Y outputs. Table 8 shows identical tPLH/tPHL values for both outputs under identical test conditions. Skew between Y and Y is typically < 0.2 ns and not specified separately, confirming synchronous assertion of true and complement states.